一种实现时序快速有效收敛的时钟树综合方案

发布时间：2018-02-02 23:21

本文关键词： 时钟树综合静态时序分析时序收敛　出处：《微电子学》2017年05期 　论文类型：期刊论文

【摘要】：针对低频下数字集成电路实现时序收敛需要插入大量缓冲器而导致芯片布线困难、运行时间较长等问题,提出了一种降低时钟树级数与增加保持时间余量相结合的时钟树综合方案。基于CSMC 0.35μm CMOS工艺,采用提出的方案,使用IC Compiler和Prime Time工具,分别完成了应用于高精度隔离型Σ-ΔADC芯片的低速数字滤波器的物理设计以及静态时序分析。结果表明,与传统方案相比,保持时间负松弛总值降低了95.62%,时序收敛所需缓冲器个数减少了约98.13%,运行时间缩短了97.25%,有效地降低了布线拥塞程度,快速有效地实现了时序收敛。
[Abstract]:In order to realize timing convergence of digital integrated circuits at low frequency, a large number of buffers need to be inserted, which leads to difficult wiring and long running time. A clock tree synthesis scheme based on CSMC 0.35 渭 m CMOS process is proposed, which combines the reduction of clock tree progression and the increase of retention time margin. Use the IC Compiler and Prime Time tools. The physical design and static timing analysis of low speed digital filter applied to high precision isolated 危-螖 ADC chip are completed respectively. The results show that compared with the traditional scheme. The total negative relaxation value of holding time is reduced by 95.62, the number of buffers needed for timing convergence is reduced by 98.13, the running time is shortened by 97.25, and the routing congestion degree is effectively reduced. The timing convergence is realized quickly and effectively.
【作者单位】：湘潭大学物理与光电工程学院;微光电与系统集成湖南省工程实验室;
【基金】：国家自然科学基金资助项目(61233010) 湖南省自然科学杰出青年基金资助项目(2015JJ1014)
【分类号】：TN402
【正文快照】： 0引言在大部分数字集成电路中,各时序元件之间的数据传输由一个同步时钟信号控制。时钟信号对集成电路的性能起着关键性的作用,也就是说,时钟信号的设计质量决定了芯片性能的好坏。时钟信号通常是整个芯片中扇出最大、通过距离最长、运行速度最快的信号,必须保证在最差的条件

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