JPEG2000中MQ高速解码器的FPGA实现研究

发布时间：2018-02-10 16:22

本文关键词： JPEG2000 MQ解码器 FPGA 高级综合　出处：《西安电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：JPEG2000标准是一种压缩性能良好的静止图像压缩标准,适用于不同类型的静止图像压缩,如自然图像、遥感图像、合成图像、医学图像等,并在不同的应用场合(如客户/服务器模式、数字图像检索、实时传输等)具有比JPEG更好的压缩性能,因而具有广阔的应用前景。ADV212是目前基于JPEG2000算法所实现的主流编解码芯片,但是其处理速度慢,并且不支持高分辨率图像数据的处理。这极大限制了JPEG2000在高速、高分辨率等场合的应用。因此,支持高速、高分辨处理的图像解码系统成为了国内外研究的焦点。在JPEG2000解码系统中,嵌入比特平面解码是其核心组成部分,包括比特平面解码和MQ解码两个核心模块。由于嵌入比特平面解码是高速解码系统实现的瓶颈,因此本文针对该问题进行了研究,并针对其核心模块MQ解码器,提出了一种零延迟、高吞吐率的MQ算术解码器结构,从而极大地提高了JPEG2000的解码速度。为了进一步提高解码器效率,本文对嵌入比特平面解码进一步研究,提出了多路并行的实现方案,使其满足实时处理的需求。本文主要研究内容为MQ解码器的结构优化以及Tier-1解码的并行调度处理设计。文中首先简要介绍了JPEG2000的核心算法,重点阐述了MQ编解码算法和EBCOT码块编解码原理。通过分析MQ解码器效率的限制瓶颈,提出了一种MQ解码器的结构改进方案,并使用Xilinx公司的Vivado-HLS高级综合工具,在Virtex-7 VC707硬件平台上实现了一种零延迟、高吞吐率的MQ算术解码器结构。该解码器能够一个时钟解码一个判决,解码器的吞吐率能达到102Mbps,所占资源不到1%。最后介绍了Tier-1解码的并行调度方案和在ISE环境下的实现。该方案实现了多路Tier-1的并行调度处理。实验结果表明,本文提出的MQ解码器的优化结构和多路Tier-1并行调度处理有效地提高JPEG2000的解码器效率,满足入口速率为100Mbps压缩图像的实时解码。
[Abstract]:JPEG2000 is a good compression performance of still image compression standard, suitable for different types of still image compression, such as natural images, remote sensing images, synthetic images, medical images, etc. And in different applications (such as client / server mode, digital image retrieval, real-time transmission, etc.) has better compression performance than JPEG, so it has a broad application prospect. ADV212 is a mainstream codec chip based on JPEG2000 algorithm. But its processing speed is slow, and it does not support the processing of high-resolution image data. This greatly limits the application of JPEG2000 in high-speed, high-resolution and other occasions. High-resolution image decoding system has become the focus of research at home and abroad. Embedded bit plane decoding is the core part of JPEG2000 decoding system. Because embedded bit plane decoding is the bottleneck of high-speed decoding system, this paper studies this problem, and aims at its core module MQ decoder, which includes two core modules: bit plane decoding and MQ decoding. An MQ arithmetic decoder architecture with zero delay and high throughput is proposed, which greatly improves the decoding speed of JPEG2000. In order to further improve the efficiency of the decoder, the embedded bit plane decoding is further studied in this paper. A multi-channel parallel implementation scheme is proposed to meet the requirements of real-time processing. This paper focuses on the structure optimization of MQ decoder and the design of parallel scheduling processing for Tier-1 decoding. Firstly, the core algorithm of JPEG2000 is introduced briefly. The MQ codec algorithm and the principle of EBCOT block coding and decoding are described in detail. By analyzing the bottleneck of the efficiency of MQ decoder, an improved scheme of MQ decoder structure is proposed, and the Vivado-HLS advanced synthesis tool of Xilinx company is used. An MQ arithmetic decoder structure with zero delay and high throughput is implemented on the Virtex-7 VC707 hardware platform. The throughput rate of the decoder can reach 102 Mbpss, which accounts for less than 1 resource. Finally, the parallel scheduling scheme of Tier-1 decoding and its implementation in ISE environment are introduced. The parallel scheduling processing of multi-channel Tier-1 is realized by this scheme. The experimental results show that, The optimized architecture of MQ decoder and multi-channel Tier-1 parallel scheduling process proposed in this paper can effectively improve the efficiency of JPEG2000 decoder and satisfy the real-time decoding of 100Mbps compressed images.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN764

【参考文献】