多位量化Sigma-Delta模数转换器的设计

发布时间：2018-02-12 08:38

本文关键词： 模数转换器 Sigma-Delta调制器多位量化 DWA 抽取滤波器　出处：《哈尔滨工业大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着MEMS陀螺数字化,智能化的未来需求,对数字陀螺接口电路的研究成为了热门,特别是对于接口电路中模数转换器(ADC)和数模转换器(DAC)的研究设计。本论文介绍了多位量化Sigma-Delta ADC的结构和性能参数,然后介绍了Sigma-Delta调制器的工作原理,并对比了一位量化和多位量化之间的优劣,根据设计指标确定了3阶3位量化全前馈结构Sigma-Delta调制器。论文对Sigma-Delta调制器的非理想因素进行了Simulink模型的建立,并对非理想因素进行了分析。最后在晶体管级对Sigma-Delta调制器进行了仿真,并对仿真结果进行了分析。在Matlab中Simulink环境下首先对Sigma-Delta调制器进行了行为级的设计与仿真。理想情况下,10MHz采样频率,128倍过采样率,Sigma-Delta调制器系统信噪比为125.4d B,有效位数达到了20.53。之后考虑了调制器系统的非理想因素,主要对积分器建立误差、运算放大器有限增益、开关非线性、KT/C噪声和运算放大器噪声进行了分析与模型的建立。考虑到由于多位量化导致反馈DAC电容失配引入的非线性,采用了Mathwork提供的Data Weighted Averaging(DWA)行为级模型,对这种抑制非线性的算法进行了行为级的仿真,在考虑所有非理想因素以及1%电容失配的情况,系统谐波失真小于100d B,有效位数是16位,符合设计要求。电路设计的时候需要重点考虑第一级积分器运算放大器的设计,以及第一级引入的噪声。采用4输入比较器组成的Flash多位量化器能够有效降低功耗。开关的设计需要重点关注开关电阻的大小以及电阻非线性的问题,避免由于开关非线性导致的系统谐波失真过大。最后整个调制器电路在CSMC 0.5um工艺,在Cadence中,加入0.5%电容失配,对采用DWA算法的调制器进行了仿真,并对仿真结果进行了分析,结果显示在采用DWA算法,调制器噪底低于-120d B,系统信噪比达到了112d B,谐波失真小于-120d B。最后本论文还设计了128倍降采样数字抽取滤波器,通带纹波小于0.01d B,阻带衰减小于-70d B。
[Abstract]:With the digitization of MEMS gyroscope and the future demand of intelligence, the research on interface circuit of digital gyroscope has become a hot topic. This paper introduces the structure and performance parameters of multi-bit quantized Sigma-Delta ADC, and then introduces the working principle of Sigma-Delta modulator. The advantages and disadvantages of one bit quantization and multibit quantization are compared. According to the design index, the three-order 3-bit quantization full-feedforward Sigma-Delta modulator is determined. The Simulink model of the non-ideal factors of the Sigma-Delta modulator is established in this paper. The non-ideal factors are analyzed. Finally, the Sigma-Delta modulator is simulated at the transistor level. The simulation results are analyzed. The behavior level of the Sigma-Delta modulator is first designed and simulated in the Simulink environment of Matlab. Ideally, the signal to noise ratio (SNR) of the Sigma-Delta modulator system is 125.4 dB and the effective bit is 125.4 dB. The number reaches 20.53.After considering the non-ideal factors of the modulator system, The error of integrator, the finite gain of operational amplifier, the nonlinear noise of switching KT / C and the noise of operational amplifier are analyzed and modeled. Considering the nonlinearity of feedback DAC capacitor mismatch caused by multi-bit quantization, In this paper, the behavior level model of Data Weighted verging DWA provided by Mathwork is used to simulate this algorithm. Considering all the non-ideal factors and the mismatch of 1% capacitance, the harmonic distortion of the system is less than 100dB, and the effective bit number is 16 bits. Meet the design requirements. The design of the first stage integrator operational amplifier needs to be considered in the design of the circuit. And the noise introduced in the first stage. The Flash multibit quantizer composed of 4-input comparator can effectively reduce the power consumption. The design of the switch needs to focus on the magnitude of the switch resistance and the problem of resistance nonlinearity. The system harmonic distortion caused by switching nonlinearity is avoided. Finally, the modulator using DWA algorithm is simulated by adding 0.5% capacitance mismatch to Cadence in CSMC 0.5um process, and the simulation results are analyzed. The results show that with the DWA algorithm, the noise level of the modulator is lower than -120dB, the SNR is 112dB and the harmonic distortion is less than -120dB. Finally, a 128-fold downsampling digital decimation filter is designed. The passband ripple is less than 0.01 dB and the stopband attenuation is less than -70 dB.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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