三维集成电路绑定前硅通孔测试技术研究

发布时间：2018-02-14 01:34

本文关键词： 三维集成电路硅通孔绑定前测试电阻开路故障泄漏故障　出处：《合肥工业大学》2015年硕士论文　论文类型：学位论文

【摘要】：基于硅通孔(Through Silicon Via,TSV)的三维集成电路(Three dimensional integrated circuit,3D IC)引起了半导体行业越来越多的关注。相比二维集成电路,3D IC具有诸多优点：功耗更低,面积更小,带宽更高,性能更好且支持异构集成等。然而,要使得3D IC产品被广泛使用,它的制造成本必须商业上可行,而良率是影响3D IC成本的最关键的因素之一。当前TSV工艺技术还不成熟,制造的TSV可能存在类似于微孔或针孔这样的缺陷,有缺陷的TSV降低了3D IC的良率,因此,需对TSV进行绑定前测试。然而,由于在绑定前TSV受到测试访问的限制,使得绑定前TSV测试变得异常困难。首先,晶圆薄化前,TSV掩埋于硅衬底中,仅仅它的前端与逻辑模块相连；其次,即使薄化后TSV的后端暴露出来,由于对探针严格的要求使得探针测试非常困难。针对上诉问题,本文以绑定前TSV为测试对象,在以下几方面进行了主要的研究工作：首先,学习三维集成电路相关知识及硅通孔工艺技术,探究引起TSV故障的原因并建立相应的故障模型。分析TSV电阻开路故障和泄漏故障的故障效应,并比较它们的异同。其次,分析现有的三种绑定前TSV测试方法—分压比较法、把TSV视为DRAM单元法、基于环形振荡器的测试方法。并着重探讨了当前基于环形振荡器的测试方法的还存在的缺点与不足。深入研究环形振荡器的测试机制并对基于环形振荡器的测试方法进行改进。最后,提出一种基于环形振荡器的绑定前TSV测试方法。首先将环形振荡器的TSV接收器分为一般反相器和施密特触发器,并比较这2种环形振荡器的测试分辨率；然后把施密特触发器作为TSV接收器引入绑定前TSV测试；为防止误测或误诊断,采用多个低电压测试TSV。基于45nm PTM CMOS工艺的HSPICE模拟结果表明,与现有同类方法相比,该方法具有更高的测试分辨率,且能测试大电容TSV和同时存在电阻开路故障和泄漏故障的TSV。
[Abstract]:The three dimensional integrated circuit 3D ICs based on silicon through Silicon (TSVT) have attracted more and more attention in semiconductor industry. Compared with 2D integrated circuits, 3D ICs have many advantages: lower power consumption, smaller area, higher bandwidth. However, in order for 3D IC products to be widely used, its manufacturing cost must be commercially feasible, and yield is one of the most important factors affecting the cost of 3D IC. The manufactured TSV may have defects such as micropores or pinholes. The defective TSV reduces the yield of 3D IC and therefore requires pre-binding testing of the TSV. However, because the TSV is restricted by test access before binding, This makes pre-binding TSV testing extremely difficult. First, the wafer thinning TSV is buried in silicon substrates, only its front end is connected to the logic module; and second, even if the thinned back end of the TSV is exposed, Due to the strict requirements of the probe, the probe testing is very difficult. In view of the appeal problem, this paper takes TSV before binding as the test object, and does the main research work in the following aspects: first of all, By studying the relevant knowledge of 3D integrated circuit and silicon through hole technology, this paper probes into the cause of TSV fault and establishes the corresponding fault model. The fault effects of TSV resistance open circuit fault and leakage fault are analyzed, and their similarities and differences are compared. In this paper, three existing pre-binding TSV testing methods, partial pressure comparison method, are analyzed, and TSV is regarded as DRAM unit method. The testing methods based on ring oscillator are discussed in detail. The testing mechanism of ring oscillator and the testing method based on ring oscillator are studied deeply and the testing method based on ring oscillator is also discussed. The method is improved. Finally, A pre-binding TSV testing method based on ring oscillator is proposed. Firstly, the TSV receiver of ring oscillator is divided into general inverter and Schmitt flip-flop, and the test resolution of these two kinds of ring oscillator is compared. Then Schmitt flip-flop is introduced into pre-binding TSV test as a TSV receiver, and several low-voltage TSVs are used to prevent mismeasurement or misdiagnosis. The HSPICE simulation results based on 45nm PTM CMOS process show that, compared with other similar methods, This method has higher test resolution and can test large capacitance TSV and TSVs with resistance open circuit fault and leakage fault at the same time.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407

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