片上温度和电容测量技术研究

发布时间：2018-02-15 22:08

本文关键词： CMOS 温度传感器动态范围失配误差可寻址 CBCM　出处：《浙江大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着半导体工业的快速发展,芯片的功耗变得越来越大,另外芯片温度的分布也不均匀,研究用于监控芯片温度热点的片上温度测量技术就显得越来越重要。片上电容测量技术既可用于建立互连线的寄生参数仿真模型又可对集成电路制造工艺进行监控,随着工艺节点的快速进步,其在学术界已受到了广泛关注。 CMOS智能温度传感器是一种片上温度测量技术。为了减小失配误差和保证较高的输出动态范围,本文在0.18um CMOS工艺下,设计并流片了一种新型CMOS智能温度传感器。和传统CMOS智能温度传感器相比,新结构通过减少电流镜的使用,以及在两种运行模式之间的切换,在军用温度范围内,可使输出达到90%动态范围的同时,减小至少66%的失配误差。 CBCM(Charge-Based Capacitance Measurement)测试结构是一种具有高精度和简单测量过程的片上电容测量技术,可寻址CBCM测试结构还具有较快的测试速度以及较高的面积利用率等优点。本文对CBCM基本结构的测量误差进行了理论分析和仿真,提出了减小测量误差的改进措施。另外,在55rnm和28nmCMOS工艺下,对可寻址CBCM测试结构进行了流片和测试。基于28rnm工艺的可寻址CBCM电容测试结构的流片,代表了这一领域的最新进展。
[Abstract]:With the rapid development of semiconductor industry, the power consumption of the chip becomes more and more large, and the temperature distribution of the chip is also uneven. It is more and more important to study the on-chip temperature measurement technology which is used to monitor the hot spot of chip temperature. On-chip capacitance measurement technology can be used not only to establish parasitic parameter simulation model of interconnection lines but also to monitor the manufacturing process of integrated circuits. With the rapid progress of process node, it has been paid more and more attention in academia. CMOS intelligent temperature sensor is a kind of on-chip temperature measurement technology. In order to reduce the mismatch error and ensure a high output dynamic range, in this paper, in 0.18um CMOS process, A new type of CMOS intelligent temperature sensor is designed. Compared with the traditional CMOS intelligent temperature sensor, the new structure is in the military temperature range by reducing the use of the current mirror and switching between the two operation modes. The output can reach 90% dynamic range while reducing at least 66% mismatch error. The CBCM(Charge-Based Capacitance measure structure is a high precision and simple measurement technique for measuring capacitance on a chip. Addressable CBCM test structure also has the advantages of fast test speed and high area utilization ratio. This paper analyzes and simulates the measurement error of CBCM basic structure, and puts forward some improvement measures to reduce the measurement error. In 55rnm and 28nm CMOS processes, the addressable CBCM test structure is tested and the flow sheet of the addressable CBCM capacitance test structure based on 28rnm process represents the latest development in this field.
【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407

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