数字自补偿电流舵型DAC建模

发布时间：2018-02-16 03:23

本文关键词： Verilog-A 电流舵数模转换器数字自补偿　出处：《北方工业大学》2015年硕士论文　论文类型：学位论文

【摘要】：高速高精度的数模转换器(DAC)是许多信号处理和通信系统至关重要的结构模块。电流舵型DAC由于自身结构的优越性成为了DAC设计者的首选。然而由于受到工艺偏差的影响产生的电流源不匹配以及高速情况下产生的时钟馈通和时序误差导致电流舵型DAC的性能受到了一定的制约。因此各种补偿和校准技术成为了设计者提高电流舵型DAC动态性能的主要方法。对电路建模是一种高速有效的设计研究方法,它既可以对电路进行辅助仿真,同时也可以对电路性能和参数进行研究,对电路的搭建和设计有一定的指导作用。因此本文以14位200MHz电流舵型DAC为对象,重点针对电流源的失配对DAC的动态范围影响这个问题,从对电路建模并采用数字自补偿技术对电路进行校准两个方面对提高DAC的性能的方法和技术进行了研究。首先,对DAC的原理进行了研究,具体的介绍和分析了常用的几种DAC的结构和优缺点,并对电流舵型DAC的三种结构进行详细的介绍、分析和比较。其次,本文重点分析了电流源的非理想因素产生机理和影响以及高速下数字时钟误差产生的来源,并分析了电流源失配对DAC的动态范围的影响。然后,针对这些失配,利用Verilog-A语言建立对应的模型,并将失配的电流源模型加入理想DAC模型中进行仿真分析,研究失配对DAC性能的影响,从而指导电路设计。针对电路失配,本文采用RSTC的DEM数字自补偿技术对电路进行校准,然后进行仿真验证。本文利用CADENCE, Verilog, Verilog-A, Matlab等EDA软件进行验证。电路整体采用数模混合仿真方式进行仿真,在输入时钟频率为200MHz,信号频率为0.9987MHz,14位理想DAC的SFDR为114dB；当电流源随机失配为0.1%情况下,DAC的SFDR为89dB。在0.1%的电流源失配电路中加入数字自补偿电路后,电路的SFDR为97dB,验证了其实用性。
[Abstract]:High speed and high precision digital-to-analog converter (DAC) is one of the most important structural modules in many signal processing and communication systems. The current-rudder DAC has become the first choice for DAC designers because of its advantages in structure. However, due to the process bias, the current rudder DAC has become the first choice for DAC designers. The mismatch of current source and clock feedthrough and timing error at high speed have restricted the performance of current-rudder DAC. Therefore, various compensation and calibration techniques have become designers to improve electrical performance. The main method of dynamic performance of current rudder type DAC. The circuit modeling is a high speed and effective design method. It can not only simulate the circuit, but also study the performance and parameters of the circuit. It can guide the circuit construction and design. So this paper takes the 14-bit 200MHz current-rudder DAC as the object. Focusing on the effect of current source mismatch on the dynamic range of DAC, the methods and techniques to improve the performance of DAC are studied from two aspects: modeling the circuit and calibrating the circuit using digital self-compensation technology. Firstly, the principle of DAC is studied, the structure, advantages and disadvantages of several kinds of DAC are introduced and analyzed in detail, and the three structures of current rudder type DAC are introduced, analyzed and compared in detail. In this paper, the mechanism and influence of non-ideal factors of current source and the source of digital clock error at high speed are analyzed, and the influence of current source mismatch on the dynamic range of DAC is analyzed. The corresponding model is established by using Verilog-A language, and the mismatched current source model is added to the ideal DAC model for simulation analysis. The effect of mismatch on the performance of DAC is studied to guide the circuit design. In this paper, the DEM digital self-compensation technology of RSTC is used to calibrate the circuit, and then the simulation is carried out. In this paper, we use EDA software, such as CADENCEE, Verilog, Verilog-Aand Matlab, to verify the circuit. When the input clock frequency is 200MHz and the signal frequency is 0.9987MHz / 14, the SFDR of the ideal DAC is 114dB, and the SFDR of the current source is 89 dB when the random mismatch of the current source is 0.1%. The SFDR of the circuit is 97 dB after adding the digital self-compensation circuit to the current source mismatch circuit of 0.1%, which verifies its practicability.
【学位授予单位】：北方工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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