低功耗数字加速度计接口ASIC芯片设计

发布时间：2018-02-25 06:30

本文关键词： ASIC 低功耗数字加速度计 Sigma-Delta　出处：《哈尔滨工业大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着时代的发展与科技的进步,微电子技术也逐渐融入到军事、民用等各个领域中,其中数字加速度计凭借精度高,噪声特性好,稳定性高和功耗低等优点,被广泛地运用到军事与民用的范畴。高性能的加速度计接口电路是保证加速度计稳定工作的基础。近年来,以智能手机,平板电脑与可穿戴智能设备为代表的便携式电子设备的快速发展与广泛普及,智能设备的续航问题成为消费者与设计者关注的焦点,因此低功耗数字加速度计接口电路的研究具有重要的研究意义与实际价值。本文从数字加速度计的工作原理与系统结构入手,对机械结构敏感单元的工作过程与信号检测的原理进行分析,并选择了方便低功耗设计的五阶带前馈结构的分布式反馈加速度计系统结构,对其在Matlab的Simulink下建立包含运放噪声、kT/C噪声、时钟抖动等非理想因素的行为级模型,得到的仿真结果为SNDR:101.5dB,ENOB:16.57dits。通过测试芯片的功耗来分析电路设计上可优化的结构问题。讨论了在模拟电路中的低功耗设计方法,噪声、动态范围等对功耗的限制,并对开关电容电路中的运算放大器做详细的功耗分析与低功耗设计。在理论与行为级的仿真的基础上,基于0.5μm CMOS工艺,在Cadence下完成对五阶低功耗数字加速度计接口电路的设计。Sigma-Delta数字加速度计接口电路系统的各个功能模块均能正常工作。电源电压为5V,仿真得到整体电路的功耗为9.4mW,量程为±2g,输出信号的噪声水平在-140dBV/Hz1/2,灵敏度320mV/g,等效输入加速度噪声0.8μg/Hz1/2。
[Abstract]:With the development of science and technology in the era of progress, microelectronic technology is gradually integrated into the military, civil and other fields, including digital accelerometer with high accuracy and good noise characteristics, high stability and low power consumption advantages, has been widely applied to military and civilian areas. High performance accelerometer interface circuit is the foundation to ensure the acceleration meter stability. In recent years, with the rapid development of intelligent mobile phone, tablet computer and smart wearable device for portable electronic devices and popularity of smart devices, battery life issues become the focus of attention of consumers and designers, so the research of low power digital accelerometer interface circuit has important significance and practical value. Starting with the working principle and system structure of the digital accelerometer, the principle and working process of signal detection of mechanical structure of the sensitive unit Analysis and selection of distributed five order feedforward feedback convenient low power design of accelerometer system structure, the establishment in the Matlab Simulink contains kT/C noise, noise amplifier, a behavioral model of the non ideal factors of the clock jitter, the obtained simulation results for SNDR:101.5dB, ENOB:16.57dits. power through the test chip analysis structure can be optimized for the circuit design. Discuss the design method of low power consumption, in the analog circuit noise, dynamic range and other restrictions on the power consumption, and low power consumption power consumption analysis and detailed design of the operational amplifier switch capacitor circuit. Based on the simulation theory and action on the 0.5 m based on the CMOS technique, the various functional modules to complete the design of.Sigma-Delta digital acceleration of five order low power digital accelerometer interface circuit Cadence interface circuit of the system can be Normal operation. The power supply voltage is 5V. The power consumption of the whole circuit is 9.4mW and the range is 2G. The noise level of the output signal is -140dBV/Hz1/2, sensitivity 320mV/g, equivalent input acceleration noise is 0.8 g/Hz1/2..

【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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