Sigma-Delta调制器及其抽取滤波器的设计与研究

发布时间：2018-02-25 06:03

本文关键词： 过采样噪声整形 Sigma-Delta调制器 CIC滤波器半带滤波器数字抽取滤波器　出处：《西安电子科技大学》2016年硕士论文　论文类型：学位论文

【摘要】：随着数字技术的不断进步,模数转换器被广泛的应用在电子技术的各个方面。现在非常流行一种叫做Sigma-Delta ADC的低速、高精度ADC,主要应用于音频信号的处理。Sigma-Delta ADC主要由调制器部分和低通抽取滤波器部分组成,使用了过采样技术、噪声整形技术和数字滤波技术。过采样和噪声整形技术可以将量化噪声大部分推向高频范围,然后再利用低通滤波器将高频噪声滤除,从而提高了信号带内的信噪比和精度。在研究了不同类型Sigma-Delta调制器的基本原理、结构以及实现后,提出总体设计方案。参数结构设定为2-1MASH结构的三阶调制器,1bit量化,过采样倍数128倍,实现16bits精度。输入信号为频率等于44KHz的正弦信号,采样频率为5.632MHz。在MATLAB下的SIMULINK中搭建系统整体架构,确定具体电路中系数因子,然后进行系统级仿真,仿真可以达到预定目标并有一定富余量。然后通过Sigma-Delta工具箱展开对电路非理想因素的分析建模,求出了可以获得较好调制效果的非理想因素的具体数值。调制器后继续研究数字抽滤波器,在分析了抽取的原理后,提出一种多级抽取的实现结构。之后重点研究了两种性能良好且应用广泛的特殊FIR滤波器:级联积分梳状滤波器以及半带滤波器。研究了原理、性质、实现结构以及优点等等。提出了一种多级结构实现128倍抽取的滤波器方案。输入信号频率为5.632MHz,经过抽取后的输出频率为44KHz,通带波纹小于0.01。首先对梳状滤波器和半带滤波器的具体结构参数、抽取倍数、阶数做出设定,并针对梳状滤波器的特性提出了一种补偿滤波器。之后通过在MATLAB中进行行为级的建模仿真,验证了这一结构的合理性。并生成Verilog代码,在ModelSim中进行抽取倍数的仿真。最后的仿真结果来看,所设计的ADC可以达到信噪比102dB,分辨率16bits的要求。数字抽取滤波器的输入频率5.632MHz,输出采样频率44KHz,通带频率20KHz,实现128倍抽取。
[Abstract]:With the development of digital technology, A / D converters are widely used in all aspects of electronic technology. Nowadays, a low speed converter called Sigma-Delta ADC is very popular. High-precision ADC, which is mainly used in audio signal processing. Sigma-Delta ADC is composed of modulator and low-pass decimation filter, and oversampling technique is used. Noise shaping technology and digital filtering technology. Oversampling and noise shaping techniques can push most of the quantized noise to the high frequency range, and then use a low pass filter to filter the high frequency noise. In order to improve the signal-to-noise ratio and precision in the signal band, the basic principle, structure and implementation of different types of Sigma-Delta modulators are studied, and the overall design scheme is proposed. The three-order modulator with a parameter structure of 2-1MASH is quantized by 1bit. The input signal is a sinusoidal signal with a frequency equal to 44kHz, and the sampling frequency is 5.632 MHz. The whole system structure is built in SIMULINK under MATLAB, the coefficient factor in the specific circuit is determined, and the system-level simulation is carried out. The simulation can achieve the predetermined goal and have a certain amount of surplus. Then the non-ideal factors of the circuit are analyzed and modeled by the Sigma-Delta toolbox. The specific values of the non-ideal factors which can obtain better modulation effect are obtained. After the modulator continues to study the digital pumping filter, the principle of the decimation is analyzed. A multistage decimation structure is proposed. Then two special FIR filters with good performance and wide application are studied: cascade integral comb filter and half band filter. In this paper, a multi-level filter with 128-fold decimation is proposed. The input signal frequency is 5.632 MHz, the output frequency is 44KHz, and the passband ripple is less than 0.01.First, the comb filter and semi-filter are compared. The specific structural parameters of the filter, The decimation multiple and order are set, and a compensation filter is proposed according to the characteristics of the comb filter. Then, the rationality of the structure is verified by the behavior level modeling and simulation in MATLAB, and the Verilog code is generated. Finally, the simulation results show that the designed ADC can meet the requirements of SNR 102 dB and resolution 16 bits. The input frequency of digital decimation filter is 5.632 MHz, the output sampling frequency is 44 kHz, the passband frequency is 20 kHz, and the decimation is 128-fold.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN761;TN713

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