基于40nm CMOS工艺的60 GHz注入锁定分频器的研究与设计

发布时间：2018-02-27 01:17

本文关键词： 注入锁定分频器锁定范围压控振荡器毫米波电感建模　出处：《山东大学》2015年硕士论文　论文类型：学位论文

【摘要】：当前的各种无线通信技术因为频谱资源日益紧张和传输速率有限而无法满足应用需求。毫米波通信技术的带宽高达5-7GHz,传输速率可实现数Gbps,是当前的研究热点。同时,CMOS器件的高频性能伴随工艺的快速发展而不断提高,低成本、高集成度、能与基带工艺相集成等优势使得CMOS器件成为设计毫米波集成电路的理想选择。压控振荡器和分频器作为锁相环频率综合器的核心部件,工作频率最高,它们的性能好坏将直接影响整个收发系统的性能。本文基于SMIC 40nm CMOS工艺,设计了应用于毫米波锁相环的压控振荡器和注入锁定分频器,主要工作和成果包括如下方面：1、利用ADS和HFSS软件,对应用于毫米波频段的无源器件电感和传输线进行了电磁仿真,优化器件尺寸以满足设计需求；建立电感的等效电路模型,方便设计优化和提高仿真精度；分析比较了常见可变电容结构的性能优劣。2、基于SMIC 40nm CMOS工艺,设计了一种应用于60GHz毫米波频率综合器的二分频注入锁定分频器。通过优化注入网络和有源及无源器件尺寸等方法,提高了注入效率。电磁仿真设计并优化无源电感以扩大锁定范围。优化版图设计减少了寄生、失配和干扰。后仿真结果表明,该分频器工作频率为55.2～61.2GHz,注入锁定范围为6.0GHz。电源电压0.8V下,功耗为5.5mW(不计缓冲放大器),核心电路面积为0.016mm2。本设计实现了低功耗、芯片面积小和宽锁定范围的目标。3、基于SMIC 40nm CMOS工艺,设计了一种低功耗宽调谐范围的压控振荡器。采用分布式电感电容结构,提高振荡频率,降低振荡所需的环路增益；优化谐振网络中电容的设计,降低相位噪声,提高调谐范围；电磁仿真无源电感,提高品质因数,降低相位噪声。后仿真结果表明,压控振荡器频率调谐范围为56.1-61.2GHz(5.1GHz,8.7%),振荡中心频率处的相位噪声为-88dBc/Hz@1MHz。电源电压0.8V下,功耗为3.3mW(不计缓冲放大器)。芯片核心面积为0.0135mm2。将压控振荡器的输出信号作为注入锁定分频器的输入信号,分频器对振荡器的输出频率实现二分频。压控振荡器和注入锁定分频器联合仿真的结果验证了相位噪声理论,表明压控振荡器和分频器的设计适用于毫米波锁相环频率综合器。
[Abstract]:The current wireless communication technology is unable to meet the needs of application because of the growing shortage of spectrum resources and the limited transmission rate. The bandwidth of millimeter wave communication technology is up to 5-7 GHz, and the transmission rate can be realized by several Gbpss, which is the current research hotspot. The high frequency performance of CMOS devices has been improved with the rapid development of technology. The advantages of low cost, high integration, and the ability to integrate with baseband technology make CMOS an ideal choice for the design of millimeter-wave integrated circuits. VCO and frequency divider are the core components of PLL frequency synthesizer. Their performance will directly affect the performance of the whole transceiver system. Based on the SMIC 40nm CMOS process, a voltage-controlled oscillator and an injection-locked frequency divider are designed for millimeter wave phase-locked loop (MMW PLL). The main work and achievements are as follows: using ADS and HFSS software, the electromagnetic simulation of passive device inductor and transmission line applied in millimeter wave band is carried out to optimize the device size to meet the design requirements, and the equivalent circuit model of inductance is established. It is convenient to design, optimize and improve the simulation accuracy, and analyzes and compares the performance of common variable-capacitor structures. 2. Based on SMIC 40nm CMOS process, An injection locking frequency divider for 60GHz millimeter wave frequency synthesizer is designed. The injection network and the size of active and passive devices are optimized. The injection efficiency is improved. Electromagnetic simulation design and optimization of passive inductor are used to enlarge the locking range. The optimized layout design reduces parasitism, mismatch and interference. The simulation results show that, The frequency of the divider is 55.2 GHz, the injection locking range is 6.0 GHz, the power consumption is 5.5 MW at 0.8 V power supply voltage (excluding buffer amplifier, the core circuit area is 0.016 mm2.This design achieves low power consumption. Based on the SMIC 40nm CMOS process, a low power and wide tuning range voltage-controlled oscillator is designed based on the small area and wide locking range of the chip. A distributed inductance capacitor structure is used to increase the oscillation frequency and reduce the loop gain required for the oscillation. The design of capacitance in the resonant network is optimized to reduce the phase noise and the tuning range is increased, the passive inductance is simulated by electromagnetic simulation, the quality factor is improved, and the phase noise is reduced. The frequency tuning range of the VCO is 56.1-61.2GHz (5.1GHz) and the phase noise at the central frequency of the oscillator is -88dBc / HzR 1MHz. The power supply voltage is 0.8V. The power consumption is 3.3 MW (excluding buffer amplifier). The core area of the chip is 0.0135 mm2.The output signal of the VCO is used as the input signal of the injection-locked divider. The phase noise theory is verified by the simulation of the voltage-controlled oscillator and the injection-locked frequency divider, which indicates that the design of the voltage-controlled oscillator and the divider is suitable for the millimeter-wave phase-locked loop frequency synthesizer.
【学位授予单位】：山东大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN772

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