新型低压LDMOS结构设计与仿真

发布时间：2018-02-28 23:02

本文关键词： 横向双扩散金属氧化物半导体场效应晶体管击穿电压比导通电阻超级结　出处：《西安电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：横向双扩散金属氧化物半导体场效应晶体管(Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor,LDMOS)由于源极、栅极、漏极这三个电极都分布在器件的同一表面,相较于纵向双扩散金属氧化物半导体场效应晶体管(Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor,VDMOS)而言,更容易与低压电路信号通过内部连接而实现集成,因此是实现功率集成电路(Power Integrated Circuit,PIC)的关键。功率集成电路(PIC)主要追求的指标是低功耗,所以要求横向双扩散MOS功率器件(LDMOS)的指标是实现高击穿电压和低比导通电阻。当前,国内外对于横向双扩散MOS功率器件主要的研究方向是:如何从新的结构,新的工艺,新的材料等方面对击穿电压和比导通电阻进行优化。本篇论文主要是从新结构方面,对阶梯状场氧化层折叠硅新型横向双扩散MOS功率器件和具有P型覆盖层超级结横向双扩散MOS功率器件这两种新型横向双扩散MOS功率器件的结构、性能进行分析与优化,并且对工艺流程进行了设计。首先,本论文提出了阶梯状场氧化层折叠硅新型横向双扩散MOS功率器件(SOFLDMOS),这种结构具有如下几种特点:第一,这种结构是将硅刻蚀成周期性折叠形状,使得栅极的导电区域增加,降低新型SOFLDMOS器件比导通电阻,这点原理类似于FinFET;第二,由于栅电极延伸到阶梯状场氧化层的表面,从而在正向导通时漂移区中产生多数载流子(电子)的积累层使得其比导通电阻降低。另外,由于新型SOFLDMOS器件是折叠形状,因此在漂移区I区的两个侧壁也会形成电子的积累,使得漂移区积累层中电子的数量剧增,从而降低新型SOFLDMOS器件的比导通电阻;第三,由于新型SOFLDMOS器件是折叠结构,在关态时通过X和Y方向引入的电场调制作用(原理类似于超级结)可以提高漂移区浓度,从而降低其比导通电阻;最后,将阶梯状场氧化层覆盖在漂移区的表面,通过阶梯状场氧化层的电场调制作用使得SOFLDMOS的表面电场在其阶梯处产生一个新的电场峰而使得表面电场分布趋于更加均匀。利用仿真软件ISE-TCAD具体分析了各种参数对SOFLDMOS性能的影响,结果表明:通过优化SOFLDMOS的主要参数,实现了当击穿电压在62V的条件下,获得较低的比导通电阻为0.74mΩ.cm~2。在相同击穿电压情况下,其比导通电阻相较于传统横向双扩散MOS功率器件结构的2mΩ.cm~2降低了63%左右。其次,本论文提出了具有P型覆盖层超级结横向双扩散MOS功率器件(P covered SJ-LDMOS),这种结构是在传统的N型缓冲层超级结横向双扩散MOS功率器件结构基础上,其超级结区的N型柱表面部分扩散(或离子注入)一层P型覆盖层,利用P型覆盖层与N型缓冲层的相互作用消除传统超级结横向双扩散MOS功率器件结构存在的衬底辅助耗尽效应,同时,由于N型缓冲层相当于一条导通路径,利用P型覆盖层的电中性作用,提高N型缓冲层的掺杂浓度从而降低了P covered SJ-LDMOS器件的比导通电阻。利用仿真软件ISE-TCAD具体分析了各种参数对P covered SJ-LDMOS性能的影响,结果表明:通过优化P covered SJ-LDMOS的主要参数,实现了当击穿电压在203V的条件下,获得4.26mΩ.cm~2的比导通电阻。在漂移区长度都为10μm的情况下,具有P型覆盖层超级结横向双扩散MOS功率器件结构的比导通电阻相较于传统超级结横向双扩散MOS功率器件结构的10.47mΩ.cm~2降低了59%左右,相较于传统具有N型缓冲层超级结横向双扩散MOS功率器件的7.46mΩ.cm~2降低了43%左右。最后,对阶梯状场氧化层折叠硅新型横向双扩散MOS功率器件与P型覆盖层超级结横向双扩散MOS功率器件这两种器件的工艺流程进行了设计,同时对工艺难点进行分析,并且给予解决方案。
[Abstract]:Lateral double diffused metal oxide semiconductor field effect transistor (Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor, LDMOS) as the source, gate, drain the three electrodes are distributed on the same surface of the device, compared to the vertical double diffused metal oxide semiconductor field effect transistor (Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor, VDMOS), and more easily low voltage circuit signal through the internal connection and integration, so is the integrated circuit power (Power Integrated Circuit, PIC). The key power integrated circuit (PIC) index is the main pursuit of low power consumption, so the lateral double diffused MOS power device (LDMOS) index is to achieve a high breakdown voltage and low conduction resistance at present, the research direction at home and abroad for lateral double diffused MOS main power device is: how to From the new structure, new technology, new materials and other aspects of the breakdown voltage and on resistance are optimized. This thesis is mainly from the new structure, the ladder shaped folding field oxide silicon new lateral double diffused MOS power devices and has the structure of P type layer super junction lateral double diffusion MOS the power device of the two new lateral double diffused MOS power device, performance analysis and optimization, and process design. Firstly, this thesis presents ladder folding field oxide silicon new lateral double diffused MOS power device (SOFLDMOS), this kind of structure has the following characteristics: first, the structure the silicon etching the periodic folded shape, the conductive gate region increase, reduce new SOFLDMOS devices on resistance, this principle is similar to FinFET; second, the gate electrode extends to the surface of terraced field oxide layer Thus, the majority of carriers in the forward conduction time in the drift region (E) of the accumulation layer makes its conduction resistance decreased. In addition, due to the new SOFLDMOS device is folded shape, so the two side wall in the drift region of the I area will be the formation of electron accumulation, the drift area increasing number of electron accumulation layer the new SOFLDMOS device so as to reduce the specific resistance; third, due to the new SOFLDMOS device is folded structure, through the electric field modulation into X and Y direction in the off state (principle similar to the super node) can improve the concentration of the drift region, thereby reducing the conduction resistance; finally, the surface of the ladder the shape of the field oxide layer in the drift region, the electric field modulation ladder field oxide layer makes the surface electric field of SOFLDMOS to produce a new electric field peak in the step of the surface electric field distribution tends to be more uniform by simulation. The software ISE-TCAD detailed analysis of the impact of various parameters on the performance of SOFLDMOS, the results show that the main parameters of the optimization of SOFLDMOS, realized when the breakdown voltage under the condition of 62V was lower than the resistance of 0.74M..cm~2. in the same breakdown voltage under the conduction resistance compared with the conventional lateral double diffusion MOS power device structure of 2m..cm~2 decreased about 63%. Secondly, this paper presents a P type super node layer lateral double diffused MOS power device (P covered SJ-LDMOS), the structure is in the N buffer layer, super node lateral double diffused MOS power device structure on the basis of the traditional surface N the column part of the super junction diffusion (or ion implantation) a layer of P covering layer, using the interaction between type P and type N overlay buffer layer to eliminate the traditional structure of super node lateral double diffused MOS power device substrate assisted consumption As far as effect, at the same time, because the N buffer layer is equivalent to a conduction path, using electrically neutral type P covering layer, improve the doping concentration of N buffer layer, which reduces the conduction resistance of P covered SJ-LDMOS device. A concrete analysis of the influence of various parameters on the performance of P covered SJ-LDMOS by simulation the software ISE-TCAD the results show that the main parameters optimization of P covered SJ-LDMOS, realized when the breakdown voltage under the condition of 203V, obtain the conduction resistance of 4.26M..cm~2. In the drift region length is 10 m, with P type structure covering layer of super node lateral double diffused MOS power devices than resistance compared with the traditional super node lateral double diffused MOS power device structure of 10.47m..cm~2 decreased by about 59%, compared with the traditional N type with buffer layer of super node lateral double diffused MOS power device 7.46m.Cm~2 is reduced by about 43% Finally, the process flow of two kinds of devices, the ladder type field oxide layer folded silicon new lateral double diffused MOS power device and the P overlay super junction double diffused MOS power device, are designed. Meanwhile, the technological difficulties are analyzed, and solutions are given.

【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386

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