基于级联偏置锁相环的宽带频率合成技术研究

发布时间：2018-02-28 23:02

本文关键词： 频率合成相位噪声锁相环级联偏置　出处：《电子科技大学》2016年硕士论文　论文类型：学位论文

【摘要】：频率合成器几乎是所有电子系统都不可缺少的一部分。低相位噪声和高频率分辨率的宽带频率合成器可广泛应用于通信、雷达以及电子测试与测量系统中。基本频率合成技术包括直接模拟频率合成技术、直接数字频率合成技术以及间接锁相环频率合成技术,高性能的宽带频率合成器为了同时实现低相位噪声和高分辨率等指标通常混合使用了多种基本频率合成技术。为了改善宽带频率合成器的相位噪声性能,本文设计了一种级联偏置锁相环结构。通过在锁相环的反馈回路中引入多级混频器级联,完全消除了锁相环反馈回路中的分频器,从而大大降低了环路带宽内的相位噪声。为了验证级联偏置锁相环的优异性能,本文中使用宽带YIG调谐振荡器(YTO)设计了一个测试电路。当参考频率固定为1600 MHz时,所设计的级联偏置锁相环鉴相频率固定为25MHz,可实现1950 MHz~5225 MHz、以50 MHz为间隔的66个频率点输出。为了获得1600 MHz的点频参考源设计了一个对100 MHz恒温晶振(OCXO)输出进行16倍频的倍频链电路。级联偏置锁相环在输出频率为5225 MHz时,测试出在带内100 kHz频偏处的相位噪声为-118 dBc/Hz。为了实现高频率分辨率的目的,本文为级联偏置锁相环设计了一个输出频率范围为1706 MHz~1750 MHz、频率分辨率小于0.1 Hz的参考频率源。当两个模块连接在一起并配以相应的自动配置算法就实现了一个输出频率范围为2106 MHz~5670 MHz、频率分辨率小于1 Hz的宽带频率合成器。参考环路的参考源是16倍频链输出的1600 MHz点频信号。在参考环路中,使用混频-分频法改善了直接数字频率合成器(DDS)的杂散性能,使用偏置锁相环的方式改善了相位噪声性能。在参考环输出频率为1728 MHz时,测试出相位噪声在带内10 kHz和100 kHz频偏处分别为-115 dBc/Hz和-121 dB/Hz。基于级联偏置锁相环的宽带频率合成器在输出频率为2123.125 GHz和5 GHz时在带内10 kHz频偏处分别测试出相位噪声为-113 dBc/Hz和-110 dBc/Hz。
[Abstract]:Frequency synthesizers are an indispensable part of almost all electronic systems. Wideband frequency synthesizers with low phase noise and high frequency resolution can be widely used in communications. In radar and electronic testing and measurement systems, basic frequency synthesis techniques include direct analog frequency synthesis, direct digital frequency synthesis and indirect phase-locked loop frequency synthesis. In order to achieve low phase noise and high resolution at the same time, high performance broadband frequency synthesizer usually uses a variety of basic frequency synthesizer technology, in order to improve the phase noise performance of broadband frequency synthesizer, In this paper, a cascade bias PLL structure is designed. By introducing a multistage mixer cascade into the PLL feedback loop, the frequency divider in the PLL feedback loop is completely eliminated. The phase noise in the loop bandwidth is greatly reduced. In order to verify the excellent performance of the cascade bias PLL, a test circuit is designed using a wideband YIG tunable oscillator. When the reference frequency is fixed at 1600 MHz, The designed cascade bias phase-locked loop has a fixed frequency of 25 MHz, and can realize the output of 66 frequency points at 50 MHz interval. In order to obtain the point frequency reference source of 1600 MHz, a 100MHz constant temperature crystal oscillator (OCXO) output is designed. Frequency doubling circuit. Cascaded bias PLL with output frequency of 5225 MHz, The phase noise at the 100 kHz frequency offset in the band is -118 dBc / Hz. in order to achieve high frequency resolution, In this paper, a reference frequency source with output frequency range of 1706 MHz~1750 MHz and frequency resolution less than 0. 1 Hz is designed for cascaded biasing PLL. When the two modules are connected together and matched with the corresponding automatic configuration algorithm, an output frequency source is implemented. A broadband frequency synthesizer with a frequency resolution of less than 1 Hz in the output frequency range of 2106 MHz~5670 MHZ. The reference source of the reference loop is 1600 MHz point frequency signal output from the 16-fold frequency chain. The spurious performance of direct digital frequency synthesizer (DDS) is improved by using mixed-frequency divider method, and the phase noise performance is improved by using bias phase-locked loop. When the output frequency of reference loop is 1 728 MHz, It is found that the phase noise is -115 dBc/Hz and -121 dB / Hz at 10 kHz and 100 kHz frequency offset in the band, respectively. The wideband frequency synthesizer based on cascaded bias PLL is tested at 10 kHz frequency offset in the band at the output frequency of 2123.125 GHz and 5 GHz, respectively. The noise is -113 dBc/Hz and -110dBc / Hz.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN74

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