高速高精度采样保持电路的研究与设计

发布时间：2018-03-01 19:27

本文关键词： 高速高精度采样保持电路折叠插值模数转换器开环时间交织　出处：《合肥工业大学》2016年硕士论文　论文类型：学位论文

【摘要】：采样保持电路(THC)位于高速模数转换器(ADC)的最前端,是高速ADC的核心模块之一。THC的作用是将外界输入的连续变化模拟信号瞬时值转换为离散信号并保持一定的时间以供后级电路进行量化和编码操作,它所能实现的精度和采样率决定了整个ADC可以达到的最高分辨率和最快转换速率,因此THC的性能对整个ADC性能的影响是决定性的。由于软件无线电、高频通信技术以及雷达等技术的推动,ADC在向着高速方向发展,这使得研究高性能THC也成为至关重要的一项工作。本文阐述了THC在高速高精度折叠插值ADC中的应用背景,分析了各种THC架构的优缺点,从速度和精度两方面讨论了THC性能提升的关切点,指明对于10位精度、1.6GSps采样率指标的折叠插值ADC,基于开环双通道时间交织结构设计的THC可以保证电路的可实现性与可靠性。本文重点分析了开环THC精度的限制因素,探讨了一些抑制电路非理想因素的办法,对模拟通路上各模块都提出了相应的线性度提升方法,比如：高线性度栅压自举开关、源极退化技术以及虚拟开关吸收电荷注入等技术。最终完成了包括高性能采样开关、输入/输出缓冲器、复位脉冲产生电路以及正／负压电荷泵在内的总体THC电路设计。引入了主控时钟技术用于缓解两个时间交织通道的采样时刻失配问题；采用带冗余结构的源跟随器设计两通道共享的输入缓冲器,使其带宽达到5.6GHz,无杂散动态范围(SFDR)超过77dB；采用全NMOS晶体管实现的全差分单级运放作为第二级缓冲器,基于共用偏置技术实现了其输出共模电压的稳定；基于高效率的交叉耦合电荷泵基本拓扑设计正压电荷泵、负压电荷泵以及复位脉冲产生电路。本文在Cadence Spectre环境下基于0.18μm CMOS工艺设计和仿真电路,采用2V单电源供电。仿真结果表明,在1.6GSps的奈奎斯特采样率下,采用相干采样,负载电容为600fF,输入800mVpp的正弦波,信号与噪声失真比(SNDR)达到72.3dB,有效位数(ENOB)超过11.7位,达到了10位1.6GSpsADC对于前端THC的性能要求。
[Abstract]:The sampling and holding circuit (THC) is at the front end of the high speed A / D converter (ADC). THC is one of the core modules of high speed ADC. The function of THC is to convert the instantaneous value of the continuous variation analog signal into discrete signal and maintain a certain time for the quantization and coding operation of the back stage circuit. The precision and sampling rate that it can achieve determine the maximum resolution and the fastest conversion rate that can be achieved by the whole ADC, so the performance of THC is decisive to the performance of the whole ADC. The development of high frequency communication technology and radar technology makes the research of high performance THC become a very important task. This paper describes the application background of THC in high speed and high precision folding interpolation ADC. This paper analyzes the advantages and disadvantages of various THC architectures, and discusses the concerns of improving THC performance in terms of speed and accuracy. It is pointed out that the THC based on open-loop dual-channel time-interleaved structure can guarantee the realizability and reliability of the circuit for the 10-bit precision 1.6 GSPS sampling rate index. The limiting factors of open-loop THC precision are analyzed in this paper. In this paper, some methods to restrain the non-ideal factors of circuit are discussed, and the corresponding linearity lifting methods are proposed for each module in the analog path, such as: high linearity gate voltage bootstrap switch, The source pole degradation technique and virtual switch absorption charge injection technology are finally completed, including high performance sampling switch, input / output buffer, etc. The overall THC circuit design including reset pulse generation circuit and positive / negative charge pump is designed. The master clock technology is introduced to alleviate the sampling time mismatch between two time interleaved channels. The source follower with redundant structure is used to design a two-channel shared input buffer, which has a bandwidth of 5.6 GHz, and no stray dynamic range (SFDR) of over 77dB.The full differential single-stage operational amplifier realized by full NMOS transistor is used as the second stage buffer. Based on the common bias technique, the output common-mode voltage is stabilized, and the barotropic charge pump is designed based on the high efficiency cross-coupled charge pump topology. In this paper, based on 0.18 渭 m CMOS process design and simulation circuit based on Cadence Spectre, the power supply of 2V single power supply is used. The simulation results show that coherent sampling is used at the Nyquist sampling rate of 1.6GSs. The load capacitance is 600fF, the sinusoidal wave of 800mVpp is input, the signal to noise distortion ratio (SNDR) is 72.3 dB, and the effective bit number (ENOB) is more than 11.7 bits, which meets the performance requirements of 10-bit 1.6GSps ADC for front-end THC.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN792

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