基于JESD204B协议的高速接收电路研制

发布时间：2018-03-01 19:30

本文关键词： JESD204B 串行接口芯片互联 VLSI设计　出处：《中国地质大学》2017年硕士论文　论文类型：学位论文

【摘要】：鉴于数据进出FPGA的速度与转换器数据处理速度不匹配的问题,FPGA公司早已探讨多年高速SerDes接口的话题,均已认识到大而快的通道的必要性,进而可以充分利用SerDes的带宽优势。在这样的背景下,JEDEC委员会于2011年发布了JESD204B协议,作为转换器行业的最新标准,其主要应用于数据转换器与逻辑器件(FPGA/ASIC)之间的高速串行接口。相比于传统的CMOS接口和LVDS接口,JESD204B接口在引脚数目、功耗等多个方面具备显著的优势,很好的解决了并行接口布局布线复杂以及系统中多芯片同步、多芯片间确定性时延的问题,为无线通信、医疗成像等现代高速信号处理领域的数据接口提供了有效的解决方案,业内一致认为基于JESD204B协议的高速串行转换器接口是通信系统继续提高数据传输速率的重要保障。JESD204B发布后,迅速引起了国际知名数据转换器厂商的重视,经过这几年的研究发展,目前ADI、TI等公司均已经发布多款内部集成基于JESD204B协议接口的芯片,但在国内暂无完全自主知识产权的产品出现,且基本上是利用特殊工艺如GaAs(砷化镓)工艺实现该接口电路。本文在深入理解JESD204B协议的基础上,提出了一种基于该协议的高速Serdes接口的接收电路设计方案,设计内容主要涵盖了协议的数据链路层和传输层。该文研究思路为严格依据协议规范,结合已有的相关芯片手册,将协议所包含的功能进行合理的模块划分,最终得到完全符合协议要求的电路结构。本方案为满足高达10Gbps的通道速率,采取四路并行设计的方法,有效降低了最高时钟频率的要求;同时,数据处理与同步控制分离的拓扑结构也显著的提高了电路的运行速度。针对于协议详细规范的初始码组同步、初始通道同步、字符替换、自同步加扰、8B10B编码等关键技术,本文均给出了具体的设计方案且进行了详细的描述。本文所提方案的各个模块均已通过Modelsim功能仿真及Design Compiler电路综合,结果表明该方案正确实现了协议规范的数据链路层和传输层的各种功能,且整体电路可以工作在250Mhz时钟频率以上,能够匹配高达10Gbps的串行通道速率,基本达到了协议的要求。该文提出了一种较为完整的JESD204B接收电路的解决方案,为国内JESD204B接口电路的自主设计提供了一种参考方案。
[Abstract]:In view of the mismatch between the speed of data entering and leaving FPGA and the speed of data processing of converters, the company has been discussing the topic of high-speed SerDes interface for many years and has realized the necessity of large and fast channels. In this context, the JEDEC Committee issued the JESD204B protocol in 2011 as the latest standard in the converter industry. It is mainly used in the high-speed serial interface between data converter and logic device FPGA / ASIC. Compared with the traditional CMOS interface and LVDS interface, JESD204B interface has remarkable advantages in many aspects, such as pin number, power consumption, etc. It solves the problems of complex layout and wiring of parallel interface, synchronization of multi-chip and deterministic delay between multi-chips in the system. It provides an effective solution for the data interface in modern high-speed signal processing fields such as wireless communication, medical imaging and so on. The industry agrees that the high-speed serial converter interface based on JESD204B protocol is an important guarantee for the communication system to continue to improve the data transmission rate. JESD204B has attracted the attention of well-known international data converter manufacturers and has been studied and developed over the past few years. At present, many internal integration chips based on JESD204B protocol interface have been released by Adi TI and other companies, but there are no completely independent intellectual property products in China. The interface circuit is realized by using special technology such as GaAs (GaAs) process. Based on the deep understanding of JESD204B protocol, this paper presents a design scheme of high-speed Serdes interface based on this protocol. The design mainly covers the data link layer and transmission layer of the protocol. In order to satisfy the channel rate of up to 10Gbps, the four-channel parallel design method is adopted to effectively reduce the requirement of the highest clock frequency. The topology of data processing and synchronization control also improves the speed of the circuit. The key technologies such as initial code group synchronization, initial channel synchronization, character replacement, self-synchronous scrambling 8B10B coding and so on, are discussed in detail. In this paper, specific design schemes are given and described in detail. Each module of the proposed scheme has been simulated by Modelsim function and synthesized by Design Compiler circuit. The results show that this scheme can realize all kinds of functions of data link layer and transmission layer correctly, and the whole circuit can work above 250 MHz clock frequency, and can match the serial channel rate of up to 10Gbps. In this paper, a more complete solution of JESD204B receiving circuit is proposed, which provides a reference scheme for the independent design of domestic JESD204B interface circuit.
【学位授予单位】：中国地质大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN702

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