基于FPGA的片上电路进化设计研究

发布时间：2018-03-02 04:33

本文关键词： 演化硬件笛卡尔遗传规划进化算法在线进化设计　出处：《河北师范大学》2017年硕士论文　论文类型：学位论文

【摘要】：随着社会的发展与科技的进步,电子系统不断趋于微型化、智能化,规模和复杂程度不断增加,与此同时,电子系统的可靠性也已经成为其发展过程中的巨大挑战,演化硬件的出现为处理这一问题提供了解决方案。演化硬件是进化算法与可编程逻辑器件的有机结合体,它能够像生物一样根据环境的变化自主、动态地调整自身结构,提高在恶劣环境下硬件的稳定性及可靠性,延长硬件的使用寿命。现场可编程门阵列(Field Programmable Gate Array,FPGA)作为可编程器件的最新发展成果,具有灵活方便、无限可重构的特性,被广泛用作为演化硬件的实现载体。将进化算法与可进化硬件电路在同一片FPGA上构成片上演化系统,是将演化硬件付诸工程应用,构成自适应和容错硬件系统的重要途径。本文研究了演化硬件的基本原理与关键技术,并在现场可编程门阵列FPGA芯上设计了NiosII嵌入式软核处理器CPU、虚拟可重构电路解码器VRC、在线评估通信模块,并由这三个分模块组成了片上电路在线进化设计平台,利用该平台进行了片上电路进化试验研究。主要研究内容如下:1.采用笛卡尔遗传规划CGP作为进化算法对电路进化设计进行研究,研究了染色体变异率与进化收敛速度之间的关系,得出了在给定的基因长度情况下的最优变异位数。2.研究了基于FPGA的片上电路进化设计平台。在FPGA芯片上利用设计的NiosII嵌入式软核处理器CPU,虚拟可重构电路解码器VRC、在线评估通信模块,完成了片上电路进化平台的构建。NiosII嵌入式软核处理器CPU执行进化算法,通过进化计算得出新一代种群;VRC虚拟可重构电路解码器对种群中的每个染色体进行解码,并在FPGA芯片上自动构建与该染色体相对应的电路;在线评估通信模块实现通过对构建的电路进行数据采集,并实时的将所采集的数据反馈到NiosII软核处理器,实现了电路的片上在线进化设计。并通过构建的平台对全加器和乘法器进行了片上电路在线进化设计试验研究。3.对同步时序电路的片上进化设计进行了研究。在设计的电路进化设计平台的基础上,对VRC虚拟可重构电路解码器进行改进。将D触发器与组合电路的VRC虚拟可重构电路解码器相结合构建了可进化时序电路的VRC虚拟可重构电路解码器;并通过改进的平台实现了时序电路的片上进化设计;利用该平台对模六计数器与1010序列检测器进行了进化设计研究。
[Abstract]:With the development of society and the progress of science and technology, electronic system is becoming more and more miniaturized, intelligent, scale and complexity. At the same time, the reliability of electronic system has become a great challenge in its development. The emergence of evolutionary hardware provides a solution to this problem. Evolutionary hardware is an organic combination of evolutionary algorithms and programmable logic devices. In order to improve the stability and reliability of hardware in harsh environment and prolong the service life of hardware, Field Programmable Gate FPGA (Field Programmable Gate Array), as the latest development achievement of programmable devices, has the characteristics of flexibility, convenience and infinite reconfiguration. It is widely used as the implementation carrier of evolutional hardware. The evolutionary hardware is put into engineering application by using evolutionary algorithm and evolutive hardware circuit on the same piece of FPGA to form the system of evolution on a chip. This paper studies the basic principles and key technologies of evolutionary hardware. NiosII embedded soft core processor, virtual reconfigurable circuit decoder, on-line evaluation communication module are designed on the FPGA core of field programmable gate array, and the on-chip circuit on-line evolution design platform is made up of these three modules. The main contents are as follows: 1. Descartes genetic programming (CGP) is used as the evolutionary algorithm to study the circuit evolution design. The relationship between the rate of chromosome variation and the rate of convergence of evolution is studied. The optimal number of variances in given gene length is obtained. 2. The design platform of on-chip circuit evolution based on FPGA is studied. The virtual reconfigurable circuit decoder based on NiosII embedded soft core processor is designed on FPGA chip. VRC, online evaluation communication module, The construction of on-chip circuit evolution platform. Nios II embedded soft core processor CPU performs evolutionary algorithm. By evolutionary calculation, a new generation of population VRC virtual reconfigurable circuit decoder is obtained to decode each chromosome in the population. The circuit corresponding to the chromosome is automatically constructed on the FPGA chip, and the on-line evaluation communication module realizes the data acquisition through the constructed circuit, and the collected data is fed back to the NiosII soft core processor in real time. The on-chip evolution design of the circuit is realized, and the on-chip circuit on-line evolutionary design of the full adder and multiplier is studied by using the constructed platform. 3. The on-chip evolutionary design of the synchronous sequential circuit is studied in this paper. Based on the design of the circuit evolution design platform, The VRC virtual reconfigurable circuit decoder is improved. The VRC virtual reconfigurable circuit decoder of evolutionary sequential circuit is constructed by combining D flip-flop with VRC virtual reconfigurable circuit decoder of combinational circuit. The on-chip evolutionary design of sequential circuits is realized by using the improved platform, and the evolutionary design of modular sixth counter and 1010 sequence detector is studied by using this platform.
【学位授予单位】：河北师范大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN47

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