基于USB的多功能JTAG编程器设计

发布时间：2018-03-02 05:26

本文关键词： 编程器 FPGA USB JTAG 边界扫描测试技术　出处：《哈尔滨工业大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着超大规模集成电路(Very Large Scale Integration,VLSI)技术的迅速发展,包括现场可编程逻辑器件(Field Programmable Gate Array,FPGA)与复杂可编程逻辑逻辑器件(Complex Programmable Logic Device,CPLD),因具有在线编程的独特功能,广泛应用于航空航天、网络通信、军用雷达、仪器仪表、工业控制、医用CT、家用电器、手机和计算机等各个领域,使传统设计方法正在进行一场巨大的变革。然而FPGA和CPLD得到广泛应用的同时也给烧写配置CPLD和FPGA的编程器提出了更高的挑战。当前,FPGA和CPLD的编程器主要有两种:一种是基于并口的,一种是基于USB高速接口的,前者由于下载速度慢加之便携式电脑已无并口已经很少使用,后者由于其更高的数据传输速率和使用的方便性使其在性能上更优越。但是由于USB接口的编程器价格昂贵,使得许多FPGA开发人员望而却步。其次编程器功能单一,不能满足使用者扩展功能的需求。本文研究并设计了基于IEEE1149.1标准的FPGA/CPLD编程器,在深度解析JTAG标准协议、边界扫描测试技术和USB总线技术的基础上,选择了Altera官方的可编程逻辑器件编程器作为研究对象,通过对其内部工作流程进行解析,得出了编程器的内部工作机制,并采用以PIC处理器为控制器,完成了编程器电路的设计,实现了对FPGA/CPLD的编程配置功能。不同于当前开发设计的可编程逻辑器件编程器,本论文中所设计的编程器硬件设计上更精简且不用另行设计上位机软件,直接采用Quartus II开发环境即可使用,另外由于本编程器采用了SPI设计JTAG状态机的方案,编程配置速度比当前的USB-Blaster更快;本编程器具有多种功能,除了具有高速编程配置可编程逻辑器件的功能能外,还具有多接口数据传输功能,并能够通过自行开发设计的软件直接操作数据传输。
[Abstract]:With the rapid development of very Large Scale Integration Large (VLSI) technology, including Field Programmable Gate FPGA (Field Programmable Logic device) and complex Programmable Logic device (CPLDG), Very Scale Integration (VLSI) technology has been widely used in aerospace industry due to its unique function of on-line programming. Network communications, military radar, instrumentation, industrial control, medical CTs, household appliances, mobile phones, computers and other fields, The traditional design method is undergoing a great change. However, while FPGA and CPLD are widely used, they also pose a higher challenge to writing programmers that are configured with CPLD and FPGA. Currently, there are two main types of programmers for FPGA and CPLD:. One is based on parallel ports, One is based on the USB high-speed interface, which is rarely used because of slow download speed and the lack of parallel ports for portable computers. The latter is superior in performance due to its higher data transmission rate and ease of use. But because of the high cost of the USB interface programmer, many FPGA developers are deterred. The FPGA/CPLD programmer based on IEEE1149.1 standard is researched and designed in this paper. Based on the deep parsing of JTAG standard protocol, boundary scan test technology and USB bus technology, this paper studies and designs a FPGA/CPLD programmer based on IEEE1149.1 standard, boundary scan test technology and USB bus technology. The Altera programmable logic device programmer is chosen as the research object. Through the analysis of its internal workflow, the internal working mechanism of the programmable logic device is obtained, and the PIC processor is used as the controller. The design of the programmable logic device circuit is completed, and the programming configuration function of FPGA/CPLD is realized. In this paper, the hardware design of the programmer is more concise and the upper computer software is not designed separately, and the Quartus II development environment can be used directly. In addition, the JTAG state machine is designed by SPI. The program configuration speed is faster than the current USB-Blaster, the programming device has many functions, besides the function of high speed programming configuration programmable logic device, it also has the function of multi-interface data transmission. And can be designed by self-development of software direct operation of data transmission.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791

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