16通道12位R-C结构SAR ADC的研究与设计

发布时间：2018-03-03 12:21

本文选题：SAR　切入点：ADC　出处：《浙江大学》2017年硕士论文　论文类型：学位论文

【摘要】：伴随着多媒体市场以及电子科学技术的快速发展,数字信号处理技术进步迅猛。但是自然界中的很多信号,比如温度、压力、声音、速度等物理量都是模拟信号,所以我们就需要模数转换器ADC(Analog-to-Digital Converter)实现数字和模拟信号的转换。MCU就是我们日常生活中所用的单片机(微控制单元Microcontroller Unit)。它集成了内处理器(CPU)、存储器(RAM、ROM)、计数器、以及I/O端口为一体的一块集成芯片。逐次逼近模数转换器(SARADC)是中速中精度的模数转换器,一般应用在8~16位,5MS/s以下的领域里。在目前的CMOS工艺下,SARADC可以实现较小的芯片面积和较低的芯片功耗,所以在速度、精度、成本以及功耗等各个方面具有综合的优势,特别适合应用于MCU的ADC接口。为了提高MCU的利用率,作为接口的ADC需要在尽量小的芯片面积下处理尽可能多的环境信号,因此本文设计了一个16通道的SARADC,主要分成DAC模块,比较器模块,SAR逻辑模块。根据应用指标的需要,确定了 DAC采用R-C结构,选择高五位用温度计编码的电容阵列,低七位用R-2R电阻梯形结构。采用此种结构,不仅可以省略采样电路从而减少芯片面积,也可以简化了电路的设计复杂度。同时在时序控制上,通过非交叠控制信号和部分延时采样技术避免了短路回路和电荷注入现象。而对于比较器模块而言,本文提出了一种有三级预防大电路加锁存比较器的结构,这种结构可以尽可能地发挥运算放大器和锁存器的特点,加快比较的速度。同时在设计的过程中,考虑了输出失调电压的消除技术。本文采用GSMC 130 nm E-flash工艺来实现12位1 Msample/s的SARADC,模拟电源3.3 V供电,数字电源1.5 V供电。版图设计之后,面积为626*558 μm2。通过实际测试验证,功耗为2mW.在单端模式下,有70个失码,DNL=+4.1/-1LSB,INL=+13/-2.5LSB,SNR=64.49 dB,SNDR=55.19 dB,ENOB=8.87 bit。在双端模式下,有 130 个失码,DNL=+1.7/-1 LSB,INL=+4.3/-6.1 LSB,SNR=163.05 dB,SNDR=51.48 dB,ENOB=8.26 bit。芯片实测结果和仿真有一定差距,本文进行了一定的分析。
[Abstract]:With the rapid development of multimedia and market of Electronic Science and technology, digital signal processing technology rapid progress. But many signals in nature, such as temperature, pressure, sound velocity and other physical quantities are analog signals, so we need an analog-to-digital converter (Analog-to-Digital ADC Converter) to achieve the conversion of digital and analog signals is used by.MCU in our daily life MCU (micro control unit Microcontroller Unit). It has integrated processor (CPU), memory (RAM, ROM), counter, and I/O port for a chip body. A successive approximation analog to digital converter (SARADC) is the medium speed and accuracy of ADC, generally used in 8~16 5MS/s, the following fields. At present CMOS technology, SARADC can achieve a smaller chip area and lower the power consumption of the chip, so the speed, accuracy, power consumption and cost etc. Have comprehensive advantages in all aspects, especially suitable for the ADC interface of MCU. In order to improve the utilization rate of MCU, ADC as the interface to deal with environmental signals as much as possible to a small chip area, so this paper designs a 16 channel SARADC, mainly divided into DAC module, comparator module, SAR logic according to the need of application module. Index, DAC was determined using R-C structure, select five high capacitance array thermometer encoding, low seven R-2R resistor ladder structure. Using this structure, not only can omit the sampling circuit so as to reduce the chip area, can simplify the circuit design complexity. At the same time in the timing control on the non overlapping part of the control signal and the delay sampling technique to avoid short circuit and charge injection phenomena. And for the comparator module, this paper proposes a three grade prevention power Lu Jiasuo Structure of the comparator, the structure can play as much as possible the operational amplifier and the characteristics of the latch, accelerate the speed of comparison. At the same time in the design process, taking into account the elimination technology output offset voltage. This paper uses the GSMC 130 nm E-flash technology to achieve 12 Msample/ s 1 SARADC 3.3 V power supply, analog power supply digital power, 1.5 V power supply. The layout design, the area is 626*558 m2. through the actual test, the power consumption is 2mW. in single ended mode, there are 70 missing codes, DNL=+4.1/-1LSB, INL=+13/-2.5LSB, SNR=64.49 dB, SNDR=55.19 dB, ENOB= 8.87 bit. in the double end mode, there are 130 missing codes, DNL=+1.7/-1 LSB. INL=+4.3/-6.1 LSB, SNR=163.05 dB, SNDR=51.48 dB, ENOB=8.26 bit. chip and the simulation results have a certain gap, this paper made some analysis.

【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

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