用于触摸屏控制电路的低功耗模数转换器设计

发布时间：2018-03-03 13:02

本文选题：触摸屏　切入点：低功耗　出处：《液晶与显示》2017年08期 　论文类型：期刊论文

【摘要】：为了降低触摸屏控制电路的功耗,本文提出了一种低功耗逐次逼近型模数转换器(SAR ADC)。对该SAR ADC所采用的电容阵列数模转换器(DAC)、比较器和逐次逼近寄存器等进行了研究与设计。首先,基于两级并串耦合电容设计电容阵列DAC结构,并设计配套的参考电平转换方案。接着,设计两级全动态比较器,并分析比较器的工作原理。然后,基于动态逻辑设计低功耗低误码逐次逼近寄存器。最后,基于180nm CMOS工艺,在1V电源电压,200kHz采样频率和96.243kHz输入频率条件下对SAR ADC进行了仿真。仿真结果表明:积分非线性误差(INL)和微分非线性误差(DNL)分别为0.222/-0.203LSB和0.231/-0.184LSB,无杂散动态范围(SFDR)为76.56dB,信噪失真比(SNDR)为61.50dB,有效位(ENOB)为9.92位,功耗为0.464μW,品质因素(FOM)值为2.4fJ/Conv.-step。本文设计的低功耗SAR ADC满足触摸屏控制电路应用要求。
[Abstract]:In order to reduce the power consumption of the touch screen control circuit, In this paper, a low power successive approximation type A / D converter is proposed. The capacitive array DAC, comparator and successive approximation register used in the SAR ADC are studied and designed. The DAC structure of the capacitor array is designed based on the two-stage parallel coupled capacitor, and the corresponding reference level conversion scheme is designed. Then, the two-stage full-dynamic comparator is designed, and the working principle of the comparator is analyzed. The low power low error code successive approximation register is designed based on dynamic logic. Finally, based on 180nm CMOS technology, The SAR ADC is simulated at the sampling frequency of 200kHz and 96.243kHz input frequency. The simulation results show that the integral nonlinear error (INLL) and the differential nonlinear error (DNL) are 0.222 / -0.203 LSB and 0.231 / -0.184 LSBrespectively, and the non-spurious dynamic range is 76.56 dB. SNDRs are 61.50dB and ENOB is 9.92 bits. The power consumption is 0.464 渭 W, and the quality factor FOM is 2.4 FJ / Conv.-Step.The low power SAR ADC designed in this paper can meet the requirements of touch screen control circuit.
【作者单位】：电子科技大学中山学院;电子科技大学计算机科学与工程学院;华南理工大学电子与信息学院;
【基金】：国家自然科学基金资助项目(No.61571196) 广东省科技计划项目(No.00760211330304099,No.2014A010103016,No.2014B090912001) 中山市科技计划项目(No.2016B2146,No.2017B1019)~~
【分类号】：TN792

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