基于冗余子级的流水线ADC校准技术研究与设计

发布时间：2018-03-04 17:01

本文选题：流水线ADC　切入点：自适应LMS算法　出处：《华南理工大学》2015年硕士论文　论文类型：学位论文

【摘要】：流水线ADC(Analog to Digital Conversion,ADC)以其高速度、高精度、低功耗等特性被广泛应用于高分辨率数字图像处理、视频处理以及宽带无线通信等领域。但是,随着集成电路工艺的发展,电源电压持续按比例缩小,运放有限增益、非线性误差、电容失配等非理想因素对流水线型ADC的性能提高带来了极大挑战。运用数字域的校准技术提高ADC的性能成为了近年的研究热点。本文分析了线性和非线性误差对流水线ADC的影响以及目前常用的校准流水线ADC线性和非线性误差的各种方法。针对基于参考ADC的数字后端校准算法中存在的一些缺点,即主信号通路和参考信号通路不同步会造成流水线ADC精度下降,同时主信号通路需要降频会引起流水线ADC设计复杂度上升,本文设计了一个精度比较高的流水线子级代替参考ADC,对流水线ADC的各个子级校准代替对整个ADC本身的校准,较好地解决了主信号通路和参考ADC信号通路不同步的缺点,且该校准系统不需要降频同步。本文在Cadence Spectre设计平台上设计并实现了冗余子级校准系统中开关电路、两相非交叠时钟电路、比较器电路、运算放大器电路、子级ADC电路和MDAC电路等关键模块。在Matlab/Simulink中搭建了16-bit采样频率为10MSPS的流水线ADC模型,仿真结果表明,当输入信号频率为4.7605MHz时,经过校准后,流水线ADC的有效位和无杂散动态范围分别由9.37-bit、59.96d B提高到了校准后的15.32-bit、99.55d B。最后利用Altera公司的Cyclone系列EP4CE22F17C6N器件进行FPGA硬件验证,当输入信号频率为4.7605MHz时,频谱分析表明流水线ADC的有效位和无杂散动态范围分别为12.73-bit和98.62d B,初步验证了基于冗余子级的后端校准算法的可行性。
[Abstract]:Pipeline ADC(Analog to Digital conversion ADC(Analog is widely used in many fields such as high resolution digital image processing, video processing and wideband wireless communication due to its high speed, high precision and low power consumption. However, with the development of integrated circuit technology, Constant proportional reduction of power supply voltage, limited gain of operational amplifier, nonlinear error, The non-ideal factors such as capacitor mismatch have brought great challenge to the performance improvement of pipeline type ADC. The application of digital domain calibration technology to improve the performance of ADC has become a hot research topic in recent years. The linear and nonlinear error pairs are analyzed in this paper. The influence of pipeline ADC and the various methods of calibrating the linear and nonlinear errors of pipeline ADC. Some shortcomings of the digital back-end calibration algorithm based on reference ADC are pointed out. That is, if the main signal path and the reference signal path are not synchronized, the accuracy of pipeline ADC will be decreased, and the need for the main signal path to reduce the frequency will lead to the increase of the complexity in the design of pipeline ADC. In this paper, we design a high precision pipeline sub-level instead of reference ADC, and replace the whole ADC with every sublevel calibration of pipeline ADC, which solves the disadvantage of the synchronization between the main signal path and the reference ADC signal path. In this paper, the switching circuit, the two-phase non-overlapping clock circuit, the comparator circuit and the operational amplifier circuit in the redundant sub-level calibration system are designed and implemented on the Cadence Spectre design platform. Pipeline ADC model with 16-bit sampling frequency of 10MSPS is built in Matlab/Simulink. The simulation results show that when the input signal frequency is 4.7605MHz, the model is calibrated. The effective bit and non-stray dynamic range of pipeline ADC are increased from 9.37-bitn 59.96dB to 15.32-bitmong 99.55dB, respectively. Finally, the FPGA hardware is verified by Altera's Cyclone series EP4CE22F17C6N devices. When the input frequency is 4.7605MHz, the frequency of input signal is 4.7605MHz. Spectrum analysis shows that the effective bit and non-spurious dynamic range of pipeline ADC are 12.73-bit and 98.62dB, respectively. The feasibility of back-end calibration algorithm based on redundant sub-level is preliminarily verified.
【学位授予单位】：华南理工大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

【参考文献】