高清视频帧内压缩电路的研究与设计

发布时间：2018-03-05 07:27

本文选题：差值　切入点：帧内压缩　出处：《沈阳工业大学》2017年硕士论文　论文类型：学位论文

【摘要】：视频压缩是近年来在视频传输和视频显示领域中最广泛采用的技术,随着4K视频的飞速发展,高清视频压缩和解压缩在视频显示的相关产品中占有越来越重要的地位。本文描述了高清视频压缩电路的设计过程和实现过程,主要完成了功能仿真的前端设计和综合、布局布线的后端实现。在前端设计过程中,创新性地采用传输视频数据的真实值和预测值的差值的方法来实现帧内压缩,确定了电路的整体结构,完成了预测模块、重建和生成差值模块、平坦化判定模块、索引颜色历史数据更新模块、预测模式选择模块、VLC(Variable length code)编码模块、码流控制模块等模块的设计。同时,在这一过程中对电路整体和各个部分进行了测试仿真和错误调试,此外还将整体放到了HDMI应用系统中进行仿真调试,最终确保了前端设计电路功能的正确。在后端实现过程中,用Cadecce平台下的RC工具对压缩电路进行综合,综合后产生的网表和时序文件导入到encounter工具中,最后在encounter下布局布线生成最终的版图。在这一系列过程中,如果发现时序有错误,则重复前端设计的过程修改设计直至没有时序错误为止。对于建立时间的错误,采用将大的组合逻辑运算拆分成在两个时钟周期内完成的方法进行修正;对于保持时间的错误,采用插入驱动单元的方法进行改正。综上所述,前端设计完成了将高清视频数据流进行实时压缩的功能,后端流程实现了从功能网表到生成可流片的版图的过程。经过最终测试,高清视频帧内压缩电路独立工作性能良好,而且在HDMI芯片系统中能够稳定工作。
[Abstract]:Video compression is the most widely used technology in the field of video transmission and video display in recent years. With the rapid development of 4K video, High-definition video compression and decompression play an increasingly important role in video display products. This paper describes the design process and implementation process of high-definition video compression circuit, mainly completes the front-end design and synthesis of functional simulation. In the process of front-end design, the method of transmitting the real value of video data and the difference between the predicted value and the real value is innovatively used to realize the intra-frame compression, the overall structure of the circuit is determined, and the prediction module is completed. Reconstruction and generation difference module, flatness decision module, index color history data update module, prediction mode selection module VLCL variable length codec module, code stream control module and so on. In this process, the whole circuit and each part are tested and debugged, in addition, the whole circuit is simulated and debugged in the HDMI application system, which ensures the function of the front-end design circuit is correct. The compressing circuit is synthesized by RC tool based on Cadecce, and the network table and timing file are imported into the encounter tool. Finally, the final layout is generated in encounter. The procedure of repeating the front-end design is modified until there are no time series errors. For the error of setup time, the method of dividing the large combinational logic operation into two clock cycles is used to correct the error. To sum up, the front-end design completes the function of real-time compression of high-definition video data stream. The back-end process realizes the process from the functional network table to the layout of the streaming chip. After the final test, the in-frame compression circuit of high-definition video has good performance independently and can work stably in the HDMI chip system.
【学位授予单位】：沈阳工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN402

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