纯整数运算分块并行Turbo编译码器的FPGA设计

发布时间：2018-03-06 16:10

本文选题：Turbo码　切入点：纯整数Log-Map算法　出处：《西南交通大学》2017年硕士论文　论文类型：学位论文

【摘要】：时至今日,距Turbo码提出已近20多年的时间,Turbo码在信道编码领域取得了不可替代的地位。在5G即将到来的今时今日,Turbo码具有继往开来的重要作用,为实现4G到5G的平稳转变具有重大的意义。本文以FPGA为设计对象,研究一种新型的基于纯整数运算下的分块并行Turbo译码器,在时代背景下谋求创新,迎合发展。首先,本文分别对Turbo码编译码端结构原理做了讲解,然后分析了几种经典的对数域简化MAP译码算法,对其性能进行了软件仿真对比,结果表明线性Log-Map算法在译码性能优良的情况下更易硬件实现;接着,本文研究了纯整数运算线性Log-Map译码算法,并与浮点数Log-Map算法与MAP算法进行了对比分析,仿真结果表明其BER性能与浮点数MAP算法相当,是一种译码性能优良且可直接用于硬件处理的实用算法;鉴于串行迭代译码延迟大的缺点,本文分别分析了滑窗译算以及两种不同初值处理方式的分块并行译码结构,并将其与纯整数译码算法相融合,软件仿真确定了基于纯整数运算下的分块滑窗算法的参数设置,为后文FPGA端的设计做好了理论基础。在前文研究的基础上,以Altera公司的Quartus II为设计环境,采用Verilog HDL编程语言对Turbo编译码器进行FPGA设计,充分利用流水线结构和并行化结构来优化设计时序。首先根据编码端的构造分模块设计,对每一个模块都进行了功能验证,给出了设计结果;随后针对纯整数分块并行译码算法在FPGA上进行了详细的设计,给出了每一模块的设计方案以及时序仿真图。最后,对译码器整体进行了功能测试和等效性能测试,结果表明本设计能够正确的完成相应的功能。本文共分为四章,第一章以信道编码发展史引入Turbo码,并对其研究现状做了陈述;第二章在分析Turbo编译码原理的基础上,重点引出了线性Log-Map算法;第三章实现了将纯整数线性近似Log-Map算法融合于滑窗和分块并行译码结构中;第四章给出了 Turbo编译码器的详细FPGA设计方案及结果分析。
[Abstract]:Turbo codes have gained an irreplaceable position in the field of channel coding for more than 20 years since Turbo codes were put forward, and Turbo codes will play an important role in carrying forward the future in the coming days of 5G. In order to realize the smooth transition from 4G to 5G, this paper takes FPGA as the design object, studies a new block parallel Turbo decoder based on pure integer operation, seeks innovation and caters to the development under the background of the times. In this paper, the structure principle of Turbo coding and decoding is explained, then several classical log-domain simplified MAP decoding algorithms are analyzed, and their performance is compared by software simulation. The results show that the linear Log-Map algorithm is easier to be implemented in hardware when the decoding performance is good. Secondly, the pure integer operation linear Log-Map decoding algorithm is studied and compared with the floating-point Log-Map algorithm and the MAP algorithm. The simulation results show that its BER performance is comparable to that of floating-point MAP algorithm, and it is a practical algorithm with excellent decoding performance and can be directly used in hardware processing. This paper analyzes the block parallel decoding structure of sliding window algorithm and two different initial value processing methods, and combines them with the pure integer decoding algorithm. The software simulation determines the parameter setting of the block sliding window algorithm based on the pure integer operation. On the basis of the previous research, taking the Quartus II of Altera Company as the design environment, using the Verilog HDL programming language to design the Turbo codec, the author designs the FPGA of the Turbo codec by using the Verilog HDL programming language. Make full use of pipeline structure and parallelization structure to optimize the design timing. Firstly, according to the construction of coding end sub-module design, each module is verified, and the design results are given. Then, the block parallel decoding algorithm of pure integer is designed in detail on FPGA, and the design scheme of each module and the timing simulation diagram are given. Finally, the function test and equivalent performance test are carried out on the whole decoder. The results show that the design can accomplish the corresponding functions correctly. This paper is divided into four chapters. The first chapter introduces Turbo codes in the history of channel coding, and describes the current research situation. Chapter 2 is based on the analysis of the principle of Turbo coding and decoding. The linear Log-Map algorithm is introduced in detail; in chapter 3, the pure integer linear approximate Log-Map algorithm is integrated into the sliding window and block parallel decoding structure; in chapter 4th, the detailed FPGA design scheme and the result analysis of the Turbo codec are given.
【学位授予单位】：西南交通大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.22;TN791

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