三维嵌入式芯核测试外壳优化方法

发布时间：2018-03-08 11:50

本文选题：三维测试外壳　切入点：硅通孔　出处：《合肥工业大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着集成电路工艺技术的发展,品体管尺寸逐渐减小,互连线的延迟超过了逻辑门的延迟,成为提升系统性能的主要瓶颈,三维集成电路(Three-Dimension Integrated Circuit,3D IC)能显著减低互连线延迟和系统功耗,成为一种有效解决互连线问题的方法。三维片上系统(Three-Dimension System-on-a-chip,3D SoC)结合了3D IC和片上系统(System-on-a-chip, SoC)的优点,逐渐成为集成电路领域的主流。3D SoC有粗[粒度划分和细粒度划分两种划分方式。在粗粒度划分中,3D SoC上的嵌入式芯核是按照二维的方法设计；在细粒度划分中,每个嵌入式芯核包含多层电路。细粒度划分的3D SoC能有效的减少时间延迟并提升性能,但给三维测试外壳的设计带来了很大困难。对测试外壳的设计直接决定了SoC的测试时间。本论文主要目的就是设计测试外壳的优化方法来减少3D SoC的测试时间,主要创新点和贡献如下：1.提出在TSVs与测试衬垫数量限制下,总测试时间和硬件开销协同优化的算法本文提出了在硅通孔(Through-silicon-vias, TSVs)数量和测试衬垫(test pad)数量限制下,减少3D SoC绑定前后总测试时间的3DTW0 (3D test wrapper optimization)算法,该算法将每条绑定前的测试外壳扫描链作为一个整体,将其分配到各电路层和绑定后的测试外壳扫描链,以减少总的测试时间和硬件开销。同时平衡绑定前和绑定后测试外壳扫描链,而不是分开优化绑定前和绑定后的测试外壳,这是本方法的一个特色。在ITC'02基准电路上的实验结果表明,与文献[24]的经典算法相比,本方法极大的降低了SoC的总测试时间,并且所用的硬件开销也不多。2.提出了在TSVs数量限制下的三维测试外壳优化算法本文基于BFD(Best Fit Decreasing)和遗传算法(Genetic Algorithm, GA),提出BGA(BFD and GA)方法在TSVs数量的约束下优化三维测试外壳,以减少三维嵌入式芯核总的测试时间。BGA方法首先利用BFD算法来平衡绑定前各条测试外壳扫描链,以减少绑定前测试时间,然后在绑定前测试外壳扫描链优化好的基础上,利用遗传算法在TSVs数量的约束下来平衡绑定后的各条测试外壳扫描链,以减少绑定后的测试时间。并且BGA方法对绑定后测试外壳的优化是在绑定前测试外壳优化的基础上,减少了扫描链重构所需的硬件开销。在ITC'02基准电路上的实验结果可知, BGA方法使SoC的测试总时间稍微有所增加,但大幅度减少了硬件开销。3.提出了减少3D SoC总测试时间的优化算法本文将减少3D SoC测试总时间为第一优化目的,利用BFD和AL (Allocate Layer)算法将扫描元素分配到测试外壳扫描链和层上。此方法首先将三维嵌入式芯核的所有扫描元素投影到一个平面上,用BFD算法将扫描元素分配到各条测试外壳扫描链,以减少绑定后的测试时间。再用提出的AL算法将扫描元素分配到各层电路中,使得绑定前各条测试外壳扫描链的长度也能够平衡,以减少绑定前的测试时间和所需TSVs的数量,并且AL算法能够使得各层电路所含的扫描元素总长度尽可能的相等。在ITC'02基准电路上的实验结果表明,本文提出的方法减少了测试总时间,并且使三维嵌入式芯核各层电路所含扫描元素的总长度更加均匀。
[Abstract]:With the development of integrated circuit technology, transistor size decreases, the interconnect delay exceeds the delay of logic gates, has become a major bottleneck to improve the performance of the system, the three-dimensional integrated circuit (Three-Dimension Integrated Circuit, 3D IC) can significantly reduce the interconnect delay and power consumption of the system, a method of a effective solution to each other line. The 3D system on chip (Three-Dimension System-on-a-chip, 3D SoC) combined with IC and 3D system on chip (System-on-a-chip, SoC) has gradually become a "coarse granularity and fine grained division two division of integrated circuit in the field of mainstream.3D SoC. In coarse granularity, embedded core 3D SoC the design is in accordance with the two methods; in the fine-grained classification, each embedded core contains a multilayer circuit. Fine grained division 3D SoC can effectively reduce the time delay and improve the performance, but It is difficult to design a three-dimensional test case. The test case design directly determines the test time of SoC optimization method. The main purpose of this paper is to design test case to reduce the test time of 3D SoC, the main innovations and contributions are as follows: 1. in TSVs is put forward and a testing pad under a number of constraints, the total test time the hardware overhead and collaborative optimization algorithm is presented in this paper through silicon vias (Through-silicon-vias, TSVs) and the number of test pads (test pad) the number of constraints, reduce the total test time before and after 3D SoC binding 3DTW0 (3D test wrapper optimization) algorithm, the algorithm will scan chain test case before each binding as a whole and distribute it to the wrapper scan chain circuit layer and binding, to reduce the test time and hardware overhead. At the same time the total balance before and after binding, binding test shell scan chain Instead, separate the test before and after optimization of shell binding binding, which is a feature of the method. The experimental results on ITC'02 benchmark circuits show that compared with the classical algorithm of [24], this method greatly reduces the total test time of SoC, and the hardware overhead is not much.2. based on the TSVs limit on the number of the three-dimensional test shell optimization algorithm based on BFD (Best Fit Decreasing) and genetic algorithm (Genetic Algorithm GA), BGA (BFD and GA) proposed method of 3D test shell optimization in the number of TSVs constraints, to reduce the three-dimensional embedded core test of general.BGA method first time using BFD algorithm to balance the test case before binding the scan chain to reduce test time and test before binding, a good case based scan chain optimization in the bound before, using the genetic algorithm in the number of TSVs about balance beam tied down The scan chain test shell after calibration, in order to reduce the test time bound. And the BGA method to optimize the binding test of the housing is based on Optimization of the binding test shell, reducing the scan chain reconfiguration required hardware overhead. Experimental results on ITC'02 benchmark circuits show that the BGA method to test the total the time of SoC increased slightly, but greatly reduces the hardware overhead of.3. is proposed to reduce the 3D SoC optimization algorithm for the total test time will be reduced by 3D SoC for the first time the total test optimization purposes, the use of BFD and AL (Allocate Layer) algorithm will scan the elements assigned to the test scan chain and shell layer. This method first all the elements of 3D embedded core scanning projection onto a plane, using the BFD algorithm will scan the elements assigned to each test case scan chain, in order to reduce the test time. Then put forward after binding AL The algorithm will scan the elements assigned to each layer in the circuit, so that the test case bound before the scan chain length to balance, to reduce the test time bound before and the required number of TSVs, the total length of the scan element and the AL algorithm can make the circuit layer contains as much as possible in the ITC'02 benchmark circuits are equal. The experimental results show that the proposed method reduces the total test time, and the total length of the three-dimensional embedded core circuit of each layer contains scanning elements more uniform.

【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407

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