基于UVM的SPI设计与验证

发布时间：2018-03-09 14:17

本文选题：SPI　切入点：UVM　出处：《西安电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着SOC(System on Chip)设计规模的快速发展和IP(Intellectual Property)的大量采用,验证已经成为了制约芯片设计的瓶颈。验证贯穿了整个芯片设计流程,高效的验证既可以保证设计功能的正确性,又能提高设计的生产率,为加速芯片上市时间提供强有力的保障。验证可以分为功能验证和时序验证两大部分。本文主要研究的是SOC验证的核心——数字功能验证。首先调研当前SoC的背景,研究的目的与意义以及国内外研究现状。证明验证的重要性。分析目前验证面临的挑战,总结当前主流的功能验证技术,提出应对这些挑战所采用的一些验证技术和方法,包括约束随机验证、覆盖率驱动验证和断言等验证方法。SystemVerilog验证语言集成了面向对象编程以及受约束的随机激励,为功能验证提供了强大的支持。UVM验证方法学是以SystemVerilog为基础所建立的一个库,它提供了一系列的接口,使得验证平台的搭建变得简单,从而能够更方便的完成验证。SPI是一种常用的标准串行接口,Si4432是一款高性能射频收发器。本文以Si4432芯片中的SPI控制接口为基础实现芯片的功能验证。通过分析SPI协议,深入研究SPI的原理和基本结构,以及SPI工作模式、SPI传输模式。采用Verilog HDL语言完成了对SPI接口的设计。本文的重点是对设计的SPI进行功能验证。先通过SPI的设计总结出了验证平台的主要架构,然后结合UVM验证方法学设计并使用硬件验证语言编写了一个验证平台。最后对验证平台进行优化。采用虚接口完成多种激励的同步,使验证平台可以同时进行寄存器的配置和正常包的发送。其次改用FIFO的形式连接组件,主要使记分板能共主动接受数据。增加注入非正常激励的功能,实现整个验证平台的完备性。通过回调的方式,完成对驱动器和监视器的改进,使验证平台能够用于多个项目设计中,从而提高了验证平台可重用性。本章最后对验证平台进行覆盖率的测试。通过观测功能覆盖率来调整验证激励的生成方式,让激励尽可能完备,使代码覆盖率和功能覆盖率都达到100%,实现验证平台的正确性并且完成对SPI设计的验证。
[Abstract]:With the rapid development of SOC(System on chip design scale and the large adoption of IP(Intellectual property, verification has become the bottleneck of chip design. Can also improve the productivity of the design, The verification can be divided into two parts: functional verification and timing verification. This paper mainly studies the core of SOC verification-digital functional verification. Firstly, the background of current SoC is investigated. The purpose and significance of the research, the status quo of research at home and abroad, the importance of proof verification, the analysis of the challenges faced by the current verification, the summary of the current mainstream functional verification technologies, and some verification techniques and methods used to deal with these challenges are put forward. The verification methods, such as constrained random verification, coverage driven verification and assertion, integrate object-oriented programming and constrained random excitation. It provides powerful support for functional verification. UVM verification methodology is a library based on SystemVerilog. It provides a series of interfaces, which make it easy to build verification platform. Therefore, it is more convenient to complete verification. SPI is a common standard serial interface, Si4432 is a high performance RF transceiver. This paper realizes the functional verification of Si4432 chip based on the SPI control interface. By analyzing the SPI protocol, this paper analyzes the SPI protocol. Deeply study the principle and basic structure of SPI, The Verilog HDL language is used to complete the design of the SPI interface. The emphasis of this paper is to verify the function of the designed SPI. Firstly, the main framework of the verification platform is summarized through the design of the SPI. Then a verification platform is designed with UVM verification methodology and hardware verification language. Finally, the verification platform is optimized, and the virtual interface is used to complete the synchronization of various excitations. The verification platform can configure registers and send normal packets at the same time. Secondly, the components can be connected in the form of FIFO, so that the scorecard can accept the data actively and increase the function of injecting abnormal excitation. The implementation of the integrity of the entire verification platform. Through the callback way, complete the improvement of the driver and monitor, so that the verification platform can be used in multiple project design, In the end of this chapter, the coverage of the verification platform is tested. The generation of validation incentive is adjusted by the coverage of observation function to make the incentive as complete as possible. Make the code coverage and function coverage reach 100, verify the correctness of the platform and complete the verification of the SPI design.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

【参考文献】