基于CMOS工艺的全芯片ESD设计

发布时间：2018-03-09 15:04

本文选题：全芯片ESD保护　切入点：ESD器件　出处：《电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：作为芯片可靠性的重要课题之一,静电放电(ESD)得到了越来越多芯片设计人员和用户的重视。特别是在半导体工艺进入亚微米尺寸后,栅氧减薄,结深变浅。这些因素都导致芯片在ESD的冲击下更加脆弱。对芯片ESD防护的迫切需求催生了大量ESD测试方法和防护方法,ESDA的成立也为ESD性能评估提供了详细标准。本文立足于全芯片的角度,从测试方法开始,详细阐述了现有ESD模型,并通过仿真和数学分析的方式证明了这些测试方法的合理性。本文还介绍了常用了的ESD器件:二极管、MOSFET和SCR。从它们的特性出发,简单介绍了各自的应用场合。二极管正向能够提供足够的导通电流能力,而方向有着更小的漏电。MOSFET四端组合能够实现不同的ESD应用,同时MOSFET的表面导通模式和双极模式有着不同的ESD保护能力。SCR有着最强的电流导通能力,但其触发电压过高、维持电压过低限制了其应用范围。本文从它们各自的工作原理触发,介绍了一些优化方法,拓宽了他们各自的应用范围。在以上器件的基础上,可以实现一些基本的ESD保护电路。保护电路可由触发电路和放电电路构成。触发电路根据触发机理又可分为上升沿触发和阈值触发。他们各自有自己的应用范围。同时放电电路可由上述ESD器件构成。不同触发电路和放电电路的组合,能够实现不同特性,克服了单个器件性能的不足,满足了不同应用范围的需求。文中利用电源钳位这一特例,介绍了在具体案例下怎么选择触发电路和放电电路的组合。从全芯片来讲,要满足各个引脚之间都存在静电放电通道,需要利用各种ESD保护电路以及放电总线构建ESD防护网络。在单电源域电路中可以使用电源轨作为放电总线。而多电源域的电路需要在每个电源域之间添加钳位电路,使每个电源域间都存在放电通道。对于混合电压接口无法使用电源轨作为放电总线,这时只能采用局部保护的方式。栅氧防护中为了避免电压过冲效应会使用到两级保护结构,为了减少两级保护结构的版图面积,可以使用Pad下的器件设计方法。
[Abstract]:As an important subject of chip reliability, electrostatic discharge (ESD) has been paid more and more attention by chip designers and users. These factors make the chip more vulnerable to the impact of ESD. The urgent demand for chip ESD protection has led to the establishment of a large number of ESD testing methods and protection methods, which also provide a detailed standard for evaluating the performance of ESD. This paper is based on the whole chip. Starting from the test methods, the existing ESD models are described in detail, and the rationality of these test methods is proved by simulation and mathematical analysis. The commonly used ESD devices, diode MOSFETs and SCRs, are also introduced in this paper. This paper briefly introduces their respective applications. The diode forward can provide enough on-current capacity, while the direction has a smaller leakage. MOSFET four-terminal combination can realize different ESD applications. At the same time, the surface conduction mode and bipolar mode of MOSFET have different ESD protection ability. SCR has the strongest current conduction ability, but its trigger voltage is too high and the maintenance voltage is too low to limit its application range. Some optimization methods are introduced, and their respective applications are broadened. On the basis of the above devices, Some basic ESD protection circuits can be realized. The protection circuits can be composed of trigger circuit and discharge circuit. The trigger circuit can be divided into rise edge trigger and threshold trigger according to the trigger mechanism. Each of them has their own application scope. The same discharge circuit may be composed of the above mentioned ESD devices. The combination of different trigger circuits and discharge circuits, Can achieve different characteristics, overcome the shortcomings of the performance of a single device, and meet the needs of different applications. In this paper, the special case of power clamping is used. This paper introduces how to select the combination of trigger circuit and discharge circuit in a specific case. It is necessary to use various ESD protection circuits and discharge bus to construct the ESD protection network. In the single power domain circuit, the power supply rail can be used as the discharge bus. The discharge channel exists between each power supply field. For the hybrid voltage interface, the power rail can not be used as the discharge bus, then only partial protection can be adopted. In order to avoid the voltage overshoot effect, the two-stage protection structure is used in the gate oxygen protection. In order to reduce the layout area of two-stage protection structure, the device design method based on Pad can be used.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN432

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