多模多标准系统中小数分频器的设计

发布时间：2018-03-14 14:06

本文选题：多模多标准　切入点：频率综合器　出处：《东南大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着各种无线通信模式的不断涌现,在一个移动终端上集成多种通信模式已成为当前无线通信技术发展的趋势,支持多模多标准的无线射频收发机也因此成为了人们研究的热点。作为无线收发机射频前端的关键模块,频率综合器不仅决定了整个收发机性能的好坏,也是实现多模多标准无线收发机全集成的关键之一。小数分频器通过改变分频比使频率综合器能提供多个高精度频率信号,是小数频率综合器中非常重要的模块。本文对多模多标准系统中锁相环频率综合器的小数分频器进行研究和设计。本文首先介绍了小数频率综合器的基本原理和组成模块,分析了各项性能指标,建立了锁相环频率综合器锁定状态的线性相位模型,给出了各模块到锁相环频率综合器输出端的噪声传递函数。根据系统要求给出了频率综合器的系统架构。在此基础上,设计了一款小数分频器,主要模块包括高速二分频器、0.5步进可编程分频器与△-Σ调制器。第一级高速二分频器工作在最高频率,电路采用源极耦合逻辑实现,具有很宽的频率工作范围。0.5步进可编程分频器由第二级高速二分频器、相位切换电路、整数可编程分频器与逻辑控制模块构成。其中,第二级高速二分频器输出四路正交信号,供相位切换电路进行切换；整数可编程分频器由6级2/3分频器级联构成,通过加入逻辑门进行分频比扩展,可实现32～127的分频比范围。逻辑控制模块通过控制相位切换的次数来实现0.5的分频比步进。△-Σ调制器采用了一种改进的MASH 1-1-1结构实现,它由三个一阶误差反馈调制器级联而成,与传统结构的MASH 1-1-1结构相比,本设计中第二级与第三级的误差反馈调制器之间增加了一个前馈连接,可同时接收前级的量化噪声和最终输出,可以提高输出序列长度以减小小数杂散,△-Σ调制器采用数字半定制方法实现。该小数分频器采用TSMC 0.18μm RF CMOS工艺设计。整个小数分频器的面积为1130μm×510μm,已成功流片,并且完成在片测试,测试结果表明：在1.8V电源电压下,小数分频器在0.8-9GHz频率范围内能够正确分频,分频比范围达到62.5～254,总的电流消耗为29mA,满足指标要求。本论文所设计的多模多标准小数分频器在无线通信、卫星导航、无线传感网等领域都具有应用价值,应用前景广阔,并对其他应用设计也具有一定的参考意义。
[Abstract]:With the emergence of various wireless communication modes, the integration of multiple communication modes on a mobile terminal has become the trend of the development of wireless communication technology. As a key module of RF front end of wireless transceiver, frequency synthesizer not only determines the performance of the whole transceiver. It is also one of the keys to realize the full integration of multi-mode and multi-standard wireless transceiver. The fractional frequency divider can provide multiple high-precision frequency signals by changing the frequency divider ratio. It is a very important module in decimal frequency synthesizer. This paper studies and designs the fractional frequency divider of PLL frequency synthesizer in multi-mode and multi-standard system. Firstly, this paper introduces the basic principle and composing module of decimal frequency synthesizer. The performance indexes are analyzed, and the linear phase model of the locked state of PLL frequency synthesizer is established. The noise transfer function from each module to the output of the PLL frequency synthesizer is given. The system architecture of the frequency synthesizer is given according to the system requirements. On this basis, a fractional frequency divider is designed. The main modules include a high speed dicusser, a 0.5 step programmable frequency divider and a-危 modulator. The first stage high speed frequency divider operates at the highest frequency, and the circuit is realized by source pole coupling logic. The step programmable frequency divider has a wide frequency range. 0.5 step programmable frequency divider consists of a second stage high speed two frequency divider, a phase switching circuit, an integer programmable frequency divider and a logic control module, in which the second stage high speed second frequency divider outputs four orthogonal signals. The integer programmable frequency divider is composed of 6 stages 2/3 frequency divider cascaded, and the frequency division ratio is expanded by adding logic gate. The logic control module realizes the frequency division ratio step of 0.5 by controlling the frequency of phase switching. The-危 modulator is implemented by an improved MASH 1-1-1 structure, which consists of three first-order error feedback modulators cascaded. Compared with the traditional MASH 1-1-1 structure, a feedforward connection is added between the second stage and the third stage of the error feedback modulator in this design, which can receive both the quantized noise and the final output of the previous stage. The output sequence length can be increased to reduce the fractional spurious, and the-危 modulator is realized by digital semi-customization. The fractional frequency divider is designed by TSMC 0.18 渭 m RF CMOS process. The area of the whole fractional frequency divider is 1130 渭 m 脳 510 渭 m. The test results show that the fractional frequency divider can divide the frequency correctly in the frequency range of 0.8-9GHz at 1.8 V power supply voltage. The frequency division ratio reaches 62.5? 254and the total current consumption is 29mA. the multi-mode and multi-standard fractional frequency divider designed in this paper has great application value in wireless communication, satellite navigation, wireless sensor network and so on. And also has certain reference significance to other application design.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN772

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