基于压控振荡器的10位ADC设计

发布时间：2018-03-16 12:51

本文选题：模/数转换器　切入点：压控振荡器　出处：《西安邮电大学》2017年硕士论文　论文类型：学位论文

【摘要】：作为脑-机接口的重要组成部分,植入式/穿戴式生物医疗电子器件承担着对生物电信号的采集、处理以及传输等任务,而模/数转换器(ADC:Analog-to-Digital Converter)则是采集系统的核心模块。考虑植入式/穿戴式的特殊应用场合,生物医疗电子器件对内部ADC的功耗和面积都有一定的要求。此外,伴随着工艺尺寸的减小,电源电压逐渐下降,传统结构的ADC在电压域进行量化的工作方式面临着日益严峻的挑战。针对以上背景,本论文设计了一种基于压控振荡器(VCO:Voltage Controlled Oscillator)的10-bit ADC,主要设计方案和创新之处包括:1.本文基于模拟-时间-数字(ATD:Analog-time-digital)的方式完成模/数转换器的设计。通过电压域信号和时间域信号的转换,使量化过程完全在时间域内完成,不仅消除了低电源电压对电压量化带来的挑战,而且显著减少了整个转换器中模拟电路模块的数量和规模,能够有效减小芯片的面积;2.本文采用两个完全相同的单端输入VCO型ADC构成全差分结构,相比单端输入的ADC结构,全差分结构具有良好的抑制共模干扰和改善非线性的能力,能够优化整个ADC的信噪比;3.为了减小芯片面积,本文采用反相器作为延迟单元来构成三级环形VCO,并利用反相器结构的延迟负反馈来产生振荡波形。本文中的VCO电路结构简单、便于调节,在不改变电路整体结构的前提下,通过对延迟级数的调节即可实现振荡周期的改变;4.在数字电路部分,本文采取10-bit全减电路将两个单端ADC的数字输出转换成单端输出。为了克服传统减法电路结构复杂、面积大、功耗高等缺点,本设计提出了一种新型的基于多米诺连接结构的二进制减法器,能够显著减少MOS管的使用数量,进而减小芯片电路的功耗和面积。整个VCO型ADC采用0.18 μm标准CMOS工艺设计实现,分别利用Cadence和Matlab对ADC电路进行设计和仿真。在1-V电源电压下,当采样速率为25KS/s时,ADC的有效位数(ENOB)是9.17bit,信噪失真比(SNDR)是57dB。包括输出驱动电路在内,整个ADC的功耗是20.19 μW,品质因数(FoM)是0.39 pJ/conversion-step。本文设计的10-bitADC有源面积为270μmx100μm,具有显著的面积优势,非常适合植入式生物医疗电子的应用。
[Abstract]:As an important part of brain-computer interface, implantable / wearable biomedical electronic devices are responsible for the collection, processing and transmission of bioelectrical signals. The ADC: Analog-to-Digital converter is the core module of the acquisition system. Considering the special application of implantable / wearable, biomedical electronic devices have certain requirements for the power consumption and area of internal ADC. With the decrease of process size, the power supply voltage decreases gradually, the traditional structure of ADC in voltage domain quantization is facing increasing challenges. In this paper, we design a 10-bit ADCs based on VCO: VCO: voltage Controlled Oscillator. The main design schemes and innovations include: 1. In this paper, A / D converter is designed based on ATD: ATD: Analog-time-digital converter. The signal in voltage domain is used to design A / D converter. And time domain signal conversion, The quantization process is completed completely in the time domain, which not only eliminates the challenge posed by low power supply voltage to voltage quantization, but also significantly reduces the number and size of analog circuit modules in the whole converter. In this paper, two identical single-terminal input VCO type ADC are used to form a fully differential structure. Compared with the single-ended input ADC structure, the fully differential structure has a good ability to suppress common-mode interference and improve the nonlinearity. The SNR of the whole ADC can be optimized. In order to reduce the chip area, the inverter is used as the delay unit to construct the three-stage annular VCO, and the negative feedback of the inverter is used to generate the oscillation waveform. The VCO circuit in this paper is simple in structure. Easy to adjust, without changing the whole structure of the circuit, the oscillation period can be changed by adjusting the delay series. In order to overcome the disadvantages of complex structure, large area and high power consumption of the traditional subtraction circuit, the digital output of two single-terminal ADC is converted into single-terminal output by 10-bit full subtraction circuit in order to overcome the disadvantages, such as complex structure, large area and high power consumption, etc. In this design, a new type of binary subtracter based on domino connection structure is proposed, which can significantly reduce the number of MOS transistors used, and then reduce the power consumption and area of the chip circuit. The whole VCO ADC is designed and implemented using 0.18 渭 m standard CMOS process. Cadence and Matlab are used to design and simulate the ADC circuit respectively. At 1-V power supply voltage, the effective bit number ENOB is 9.17 bit and the signal-noise-distortion ratio is 57 dB at the sampling rate of 25 KS / s, including the output drive circuit. The power consumption of the whole ADC is 20.19 渭 W and the quality factor is 0.39pJ / Conversion-step.The active area of the 10-bit ADC designed in this paper is 270 渭 mx100 渭 m, which is very suitable for the application of implanted biomedical electronics.
【学位授予单位】：西安邮电大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

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