图像传感器中高精度高速度ADC的研究与设计

发布时间：2018-03-18 01:20

本文选题：图像传感器　切入点：逐次逼近模数转换器　出处：《吉林大学》2015年硕士论文　论文类型：学位论文

【摘要】：图像传感器是一种将光学图像转换为电子信号的设备，是集像素阵列、模拟电路、数字电路于一体的数混合集成电路。根据最新的市场调查报告，从2014年到2020年，图像传感器产业将以10.6%的年均复合增长率快速增长，在2020年预计将达到160亿美元的市场价值。在这庞大的市场中有很多领域需要高速图像传感器，比如科学研究、撞击测试、高速扫描、机器视觉、军事研究等等。通常来说，图像传感器中应用的是斜坡模数转换器，然而由于其自身架构的局限性，斜坡模数转换器成为了高速图像传感器设计的瓶颈。在众多其他类型的模数转换器中，逐次逼近模数转换器由于高精度、高速度、低功耗和面积小等优势而与图像传感器契合度更高，是设计高速CMOS图像传感器时的首选。因而本课题在高速图像传感器的应用背景下，设计了一款10bit20MS/s的全差分SAR ADC。它主要由采样保持电路、比较器、异步时钟产生电路、SAR逻辑控制模块和DAC组成。通过对架构的优化，本课题设计的逐次逼近模数转换器相比于传统的逐次逼近模数转换器要减少一半的电容，并且DAC中电容对应的开关偏转平均功耗仅为传统架构消耗能量的18.74%。本论文设计的SAR ADC芯片在0.18um的CMOS工艺下，芯片面积为750x135um2；在1.8V的电源电压下，芯片功耗为750uW。完成SARADC的版图设计后，提取寄生，当输入信号频率为566.4kHz时，得到的仿真结果如下：有效位数ENOB为9.89bit，信噪失真比SNDR为61.33dB，无杂散动态范围SFDR为77.09dB。此外，还通过工艺角的仿真验证了上述结果的可靠性。对SARADC进行流片，并搭建测试平台，，当输入信号频率为112kHz时，测得的结果如下：有效位数ENOB为8.63bit，信噪失真比SNDR=53.76dB，无杂散动态范围SFDR为67.31dB。
[Abstract]:Image sensor is a device for converting optical image into electronic signal. It is a digital hybrid integrated circuit that integrates pixel array, analog circuit and digital circuit. According to the latest market research report, from 2014 to 2020, The image sensor industry is expected to grow rapidly at an annual compound growth rate of 10.6% and is expected to reach market value of $16 billion in 2020. There are many areas in this huge market that require high-speed image sensors, such as scientific research and impact testing. High-speed scanning, machine vision, military research, etc. Generally speaking, slope A / D converters are used in image sensors. However, because of the limitations of their own architecture, sloping analog-to-digital converters have become the bottleneck in the design of high speed image sensors. Because of the advantages of high precision, high speed, low power consumption and small area, the successive approximation A / D converters are more suitable for image sensors, which is the first choice in the design of high speed CMOS image sensors. Therefore, under the background of high speed image sensor, a 10 bit 20 MS / s fully differential SAR ADCs is designed. It consists of sampling and holding circuit, comparator, asynchronous clock generator circuit and DAC logic control module. Compared with the conventional successive approximation A / D converters designed in this paper reduce the capacitance by half and the average power consumption of the switches corresponding to the capacitors in the DAC is only 18.74% of the energy consumed by the traditional architecture. The SARADC chip designed in this paper has an area of 750x135um2 under 0.18um CMOS process, and the chip power consumption is 750uW. after the layout design of SARADC is completed, the parasitism is extracted. When the input signal frequency is 566.4kHz, The simulation results are as follows: the effective bit number (ENOB) is 9.89 bit, the signal-noise-distortion ratio (SNDR) is 61.33 dB, and the non-spurious dynamic range (SFDR) is 77.09 dB. In addition, the reliability of the above results is verified by the simulation of the process angle. When the input signal frequency is 112kHz, the results are as follows: the effective bit number ENOB is 8.63 bit, the signal-noise-distortion ratio is 53.76 dB, and the SFDR is 67.31 dB in the non-spurious dynamic range.
【学位授予单位】：吉林大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792;TP212

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