面向拥塞控制的片上网络设计与实现

发布时间：2018-03-20 05:23

本文选题：拥塞　切入点：拓扑结构　出处：《西安电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：世界数字化进程的不断推进对集成电路的性能提出了更高的要求。集成电路仍以摩尔定律迅猛发展,单芯片上集成的晶体管数量不断增加。集成电路中功能的集成化使得大量由不同设计公司与厂商的设计模块(IP核)以SoC的设计方法被集成在单芯片上。各IP核之间通过信息交换和数据处理完成用户所要求的系统功能。共享总线之类的长的全局互连通信形式不能适应众多IP之间对于更高通信性能的需求,这使得数字系统的性能越来越受到通信能力的限制。片上网络(NoC,Network-on-Chip)是多核SoC中的通信结构,负责众多IP核之间的通讯。它来源于Internet中的分布式路由,通讯节点与数据链路由众多用户所共享,具有带宽高、功耗低、易于扩展的特点。本文针对二维Mesh结构片上网络的拥塞问题进行了研究,分别从拓扑结构、路由算法、数据注入控制三个方面对片上网络进行改进,以缓解网络中的拥塞。首先,分析了二维Mesh结构片上网络的不足设计了分流拓扑结构,该结构利用边缘路由节点中未被使用的I/O端口,增加了数据通路以降低拥塞。所设计的重定向算法实现对分流拓扑结构中新增路径的使用。其次,分析了二维Mesh结构片上网络路由节点拥塞信息,并基于转弯模型和拥塞信息实现了自适应性路由算法。最后,设计了数据注入控制逻辑,通过调整注入率减少拥塞。本文采用VerilogHDL完成了电路的RTL级设计,设计完成后在Modelsim下对4×4规模的分流拓扑结构片上网络进行功能仿真,实现了预期的功能。在标准测试平台中以不同的流量模式对设计电路进行了测试。与采用DOR算法的Mesh结构片上网络对比,本文设计的片上网络在Random、Transpose1、Transpose2、Shuffle、Butterfly、Bit_reversal流量模式下的饱和吞率分别提升6.6%、25.6%、29.8%、14.8%、32.5%、23.5%。在SMIC 65nm工艺库下综合后表明,电路在300MHz时钟频率下能满足时序要求。此时综合网表面积为991Kμm2,与采用DOR算法的Mesh结构片上网络相比增加了4.5%。结果表明,本文设计的基于拥塞控制的片上网络在性能提升的同时只增加了较少的硬件开销。
[Abstract]:The continuous progress of digitization in the world has put forward higher requirements for the performance of integrated circuits. Integrated circuits are still developing rapidly with Moore's law. The number of transistors integrated on a single chip has been increasing. The integration of functions in integrated circuits has led to a large number of IP cores from different design companies and manufacturers) being integrated on a single chip by the method of SoC. Long global interconnect communication forms such as shared bus can not meet the needs of many IP for higher communication performance. This makes the performance of digital system more and more limited by the communication ability. The network on chip (NOC) is a communication structure in multi-core SoC, which is responsible for the communication between many IP cores. It comes from the distributed routing in Internet. Communication nodes and data links are shared by many users, with the characteristics of high bandwidth, low power consumption and easy expansion. In order to alleviate the congestion in the network, the data injection control is improved in three aspects. Firstly, the insufficiency of the two-dimensional Mesh on-chip network is analyzed and the shunt topology is designed. This structure uses the unused I / O port in the edge routing node to increase the data path to reduce congestion. The proposed redirection algorithm realizes the use of the new path in the shunt topology. The congestion information of network routing nodes on a two-dimensional Mesh structure is analyzed, and the adaptive routing algorithm is implemented based on the turning model and congestion information. Finally, the data injection control logic is designed. By adjusting the injection rate to reduce congestion, this paper uses VerilogHDL to complete the RTL level design of the circuit. After the design is completed, the 4 脳 4 scale shunt topology on-chip network is simulated under Modelsim. The design circuit is tested in different flow modes on the standard test platform, and compared with the Mesh structure using DOR algorithm. The saturated swallowing rate of the network designed in this paper under the Random-transpose 1 / transpose _ 2Shuffle2 / Butterfly/ Bitreversal flow mode is increased by 6.6and 25.6g / 25.629.8B / 32.5g / 23.5respectively. It is shown by the synthesis under the SMIC 65nm process library that, The circuit can meet the timing requirements at 300MHz clock frequency. The integrated network surface area is 991K 渭 m ~ 2, which is 4.5 more than that of the Mesh structure using DOR algorithm. The results show that, The congestion control-based on-chip network designed in this paper increases the performance of the network with less hardware overhead.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47

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