嵌入PLL大模板卷积ASIC物理设计

发布时间：2018-03-21 11:34

本文选题：时序优化　切入点：数模混合　出处：《华中科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：集成电路后端设计是指将已完成验证的前端代码设计转化为可用于生产制造的物理版图文件,是连接芯片设计与芯片制造的重要环节。其具体工作流程为:将前端设计代码基于某一种生产工艺进行逻辑综合、布局布线、时序分析及物理验证,最终得到功耗和时序符合设计要求并可以进行流片的版图文件。本文介绍了嵌入PLL(锁相环)大模板卷积ASIC的物理设计过程,着重解决了PLL的调用和数模混合芯片时序优化、布局布线及物理验证等问题。总的设计流程为:首先,建立PLL的物理模型,实现后端设计过程中调用;其次,在顶层代码加入PLL数字控制逻辑,定义互联关系并分析接口时序信息,完成物理综合;然后,对嵌入PLL的数模混合版图进行布局规划,电源规划,时钟树综合,布线优化;最后,对生成的版图文件进行物理规则验证。在时序优化上,考虑PLL嵌入问题,根据互连信息分析PLL嵌入路径时序。由于PLL模拟IP没有详细的内部时序文件,所以对嵌入路径时序约束时,整体考虑PLL的启动参数,以保证芯片的时序约束的合理性。在PLL物理模型建立上,首先根据数模混合设计要求,对原芯片版图进行IP化修改,然后抽取该物理版图的lef文件,最后通过IP版图文件和LEF信息创建物理模型,以实现ASIC布局规划时对PLL模拟IP的调用。在布局规划上,区别于传统数字后端的布局流程。首先根据数模接口的连线问题和模拟IP物理信息,确定嵌入PLL的摆放位置,然后对数模混合版图相邻位置进行隔离处理,阻止噪声传播,以实现对电路的静电保护。最后对数字部分进行合理的布局规划。完成布局布线设计后,得到一个低功耗和时序最优的版图文件,对该文件进行物理验证以保证其符合生产设计规则。然后,将完成验证的版图数据进行后功能仿真。最终版图仿真结果表明,芯片最高工作时钟125MHz,功耗647mw,管脚数目97,面积3.742mm*3.746mm,能够以40*32*8bit模板对512*512*8bit@110帧图像进行实时卷积运算,输出结果位宽27bit,芯片数据通过率达到230Mb/s,实现了预定技术指标。目前该设计已经提交流片。
[Abstract]:Integrated circuit back-end design refers to the conversion of a verified front-end code design into a physical layout file that can be used in production and manufacturing. It is an important link between chip design and chip manufacturing. Its specific work flow is: the front-end design code is based on a certain production process for logic synthesis, layout and wiring, timing analysis and physical verification, Finally, the power consumption and timing can meet the design requirements and the layout file of the streaming chip can be carried out. This paper introduces the physical design process of embedded PLL (PLL) large template convolutional ASIC, and emphatically solves the call of PLL and the timing optimization of digital-analog hybrid chip. Layout, routing and physical verification. The overall design flow is as follows: firstly, the physical model of PLL is established to realize the call in the back-end design process; secondly, the PLL digital control logic is added to the top-level code. Define interconnections and analyze interface timing information to complete physical synthesis. Then, layout planning, power planning, clock tree synthesis, routing optimization of digital-analog mixed layout embedded in PLL. To verify the physical rules of the generated layout file. In timing optimization, considering the PLL embedding problem, analyzing the PLL embedded path timing according to the interconnection information. Because the PLL simulation IP does not have the detailed internal timing file, So when we embed path timing constraints, we should consider the starting parameters of PLL as a whole to ensure the rationality of timing constraints. In the establishment of PLL physical model, the original chip layout is modified by IP according to the requirement of mixed digital-analog design. Then the lef file of the physical layout is extracted, and finally the physical model is created by IP layout file and LEF information, so as to realize the call to PLL to simulate IP in the ASIC layout planning. The layout flow is different from the traditional digital back-end. Firstly, according to the connection problem of digital-analog interface and the physical information of analog IP, the location of embedded PLL is determined, and then the adjacent position of digital-analog mixed layout is isolated to prevent the noise from spreading. In order to achieve electrostatic protection of the circuit. Finally, the digital part of the reasonable layout planning. After the completion of the layout and wiring design, a low power consumption and timing optimal layout file, The physical verification of the file is carried out to ensure that it conforms to the production design rules. Then, the post-functional simulation of the completed layout data is carried out. The final layout simulation results show that, The highest working clock of the chip is 125 MHz, the power consumption is 647 MW, the number of pins is 97, and the area is 3.742mm / 3.746mm. The chip can perform real-time convolution operation on 512121212bit 8bit @ 110 frame image with 40m 32mm 8bit template. The output result is 27 bit wide and the pass rate of chip data is 230 MB / s, which has achieved the predetermined technical target.
【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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