基于ATPG的电路抗老化输入矢量控制研究

发布时间：2018-03-22 09:24

本文选题：老化　切入点：ATPG　出处：《合肥工业大学》2017年硕士论文　论文类型：学位论文

【摘要】：随着当前集成电路特征尺寸不断减小,在带来频率功耗等性能的提升的同时,一些严重的电路可靠性问题也逐渐显现。其中负偏置温度不稳定性(Negative Bias Temperature Instability, NBTI)因为会显著导致PMOS的栅极阈值电压上升,被认为是产生电路老化现象的主要物理效应之一。在最为极端的模型中,在10年内由NBTI效应导致的电路时延增长量预测值最大为20%。通过减轻NBTI,可以有效缓解集成电路的老化效应,提高集成电路的可靠性。逻辑门的输入状态会对电路的老化效应产生直接影响,因而集成电路待机模式下的输入矢量也会对电路的老化状态有很大影响,本文由此提出一种基于门故障插入的输入矢量控制方法。首先,根据逻辑门所经过的关键路径数量的不同,在整个电路中先提取出对老化效应影响较大的关键逻辑门,避免了对整个电路进行抗老化防护带来的过大的额外面积和功耗开销。在提取的关键门集合中,插入根据一定规则放置的固定故障,最终由这些固定故障生成的输入矢量可以使得相应逻辑门电路处于老化恢复状态。同时在插入固定故障时考虑了晶体管的堆叠效应,大大减少了实际需要插入的故障数量,仿真数据显示在不同测试电路中的插入故障数均减少到之前的50%以上。得到完整的插入故障列表后,通过自动向量生成工具(Automatic Test Pattern Generation, ATPG)生成的初步的抗老化输入矢量集合。对这些输入矢量集合进行进一步的筛选以得到最优输入矢量。基于门故障的抗老化输入矢量控制方法对于不同的电路需要进行各自相应的计算,得到不同的输入矢量,因此需要加入专门输入控制电路以实现该抗老化方法,本文在板级和芯片级分别设计了硬件实现电路,可以在电路的待机模式下自动加载相应的抗老化输入矢量,同时在活动模式下不对输入端口的正常活动造成干扰。为测试产生的抗老化输入矢量对电路的防护效果,本文提出了一种基于C++程序的测试电路建模和静态时序分析方法。通过读取测试电路的网表文件,建立电路的逻辑门级的时延模型,并通过深度优先遍历和路径拓扑排序的方法将电路中所有存在路径提取出,从而在电路的不同路径上应用NBTI模型进行老化时延的计算。在对ISCAS85测试电路的实验中表明该方法相较于随机输入矢量方法有17%的时延改善量。
[Abstract]:With the decreasing of the feature size of the current integrated circuit, the frequency power consumption and other performance are improved, at the same time, Some serious circuit reliability problems are emerging, including negative bias temperature instability and negative Bias Temperature stability (NBTI), which can significantly increase the gate threshold voltage of PMOS. Is considered to be one of the main physical effects of circuit aging. In the most extreme models, The predicted value of delay growth caused by NBTI effect in 10 years is 20. By mitigating NBTIs, the aging effect of integrated circuits can be effectively alleviated. To improve the reliability of integrated circuits, the input state of logic gates will have a direct impact on the aging effect of circuits, so the input vectors in standby mode of integrated circuits will also have a great impact on the aging state of circuits. In this paper, an input vector control method based on gate fault insertion is proposed. Firstly, according to the number of critical paths passed by logic gates, the key logic gates which have a great influence on aging effect are first extracted in the whole circuit. The extra area and power cost caused by anti-aging protection of the whole circuit are avoided. In the extracted key gate set, a fixed fault is inserted according to certain rules. Finally, the input vectors generated by these fixed faults can make the corresponding logic gates in the aging recovery state. At the same time, the stacking effect of transistors is taken into account in the insertion of fixed faults, which greatly reduces the number of actual faults that need to be inserted. Simulation data show that the number of insert faults in different test circuits is reduced to more than 50% of the previous ones. The initial set of anti-aging input vectors generated by automatic Test Pattern Generation (ATPGs) is used to obtain the optimal input vectors by further screening these sets of input vectors. The anti-aging input vectors based on gate faults are obtained. For different circuits, the quantity control method needs to do their own calculation. Different input vectors are obtained, so it is necessary to add special input control circuit to realize the anti-aging method. In this paper, the hardware implementation circuit is designed at the board level and the chip level, respectively. The anti-aging input vector can be automatically loaded in the standby mode of the circuit, and the normal activity of the input port can not be interfered with in the active mode. In this paper, a method of modeling and static timing analysis of test circuit based on C program is proposed. By reading the network table file of the test circuit, the logic gate delay model of the circuit is established. Furthermore, all existing paths in the circuit are extracted by depth-first traversal and path topology sorting. The NBTI model is used to calculate the aging delay in different paths of the circuit. The experimental results of the ISCAS85 test circuit show that the proposed method can improve the delay by 17% compared with the random input vector method.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN40

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