硅基微波低噪声放大器集成电路设计

发布时间：2018-03-22 09:25

本文选题：低噪声放大器　切入点：双输入　出处：《电子科技大学》2017年硕士论文　论文类型：学位论文

【摘要】：随着无线技术的深度发展,低频的频谱资源已非常匮乏,往更高频率发展是大势所趋。更高频段的无线通信有更宽的带宽,更高的信道容量,更大的数据速率等诸多好处。而低噪声放大器是接收链路的第一个有源放大模块,它将信号进行放大,并尽可能少引入噪声,对信号的判别有着举足轻重的影响。并且随着硅基集成电路工艺的发展,栅长不断减小,特征频率不断提升,使其也能满足微波电路的设计要求,再者硅基集成电路有低成本、低功耗、高集成的优势。所以对硅基微波低噪声放大器集成电路进行研究有重大意义。针对微波集成电路设计的流程问题,本文叙述了工艺选择的过程,确定晶体管栅长、栅宽、栅指的尺寸与偏置电压的大小,并在HFSS中建立工艺模型,以满足微波电路电磁仿真的需要。采用将HFSS中电感建模仿真,提取S参数与工艺库中同尺寸电感S参数对比的方式来初步验证工艺模型的准确性。另外本文总结了硅基微波低噪声放大器集成电路设计的经验。针对传统低噪声放大器噪声系数大、功耗高的问题,本文设计了一款基于CMOS 180nm工艺的Ku波段单端低噪声放大器芯片。第一级采用变压器耦合双输入结构。测试结果表明最高增益为在17.5GHz的18dB,最小的噪声系数为在17.4GHz的3.29dB,并且在1.8V供电电压下仅消耗了7mA电流。这比传统的两级共栅结构的增益15dB提高了10%,噪声系数4dB降低了18%。芯片测试的输入1dB压缩点为-12dBm,所占面积为0.48mm~2。设计表明:双输入结构对增大增益、降低噪声系数有明显的作用。针对单端电路封装后受金丝键合影响严重的问题,本文设计了一款基于CMOS 180nm工艺的Ku波段差分低噪声放大器芯片。第一级采用电容交叉耦合双输入结构。设计结果表明该放大器能较好抑制金丝键合影响,有较好的工艺角性能。另外在性能满足设计指标的前提下,该放大器采用了全新的矩形螺旋电感,使该芯片面积比单端低噪声放大器芯片面积减小了70%,为0.144mm~2。
[Abstract]:With the deep development of wireless technology, the low frequency spectrum resources have been very scarce, it is the trend to develop higher frequency. The higher frequency band wireless communication has wider bandwidth, higher channel capacity, The LNA is the first active amplification module in the receiving link, which amplifies the signal with as little noise as possible. With the development of silicon based integrated circuit technology, the gate length is decreasing and the characteristic frequency is increasing, so that it can meet the design requirements of microwave circuit, and the silicon based integrated circuit has low cost. Because of the advantages of low power consumption and high integration, it is of great significance to study the silicon based microwave low noise amplifier integrated circuits. In view of the process of microwave integrated circuit design, this paper describes the process of process selection and determines the gate length of transistors. The width of the gate, the size of the gate finger and the bias voltage, and the process model in HFSS are established to meet the needs of electromagnetic simulation of microwave circuits. The inductance in HFSS is modeled and simulated. In order to verify the accuracy of the process model, S parameters are extracted and compared with the same size inductors in the process library. In addition, the experience of silicon based microwave low noise amplifier IC design is summarized in this paper. The sound amplifier has a large noise coefficient. The problem of high power consumption, In this paper, a Ku band single ended low noise amplifier chip based on CMOS 180nm process is designed. In the first stage, transformer coupled dual input structure is used. The test results show that the maximum gain is 18 dB of 17.5GHz and the minimum noise coefficient is in 17.4GHz. 3.29 dB, and only consumes 7mA current at 1.8 V supply voltage. This is 10 times higher than the gain 15dB of the traditional two-stage common-gate structure, and the noise coefficient 4dB is reduced by 18. The input 1dB compression point of chip test is -12 dBmand the area is 0.48 mm / 2. The design shows that:. Double input structure pair increases gain, Reducing the noise coefficient has obvious effect. In view of the problem that the single end circuit is seriously affected by the gold wire bonding after the single terminal circuit is encapsulated, In this paper, a Ku-Band differential low noise amplifier chip based on CMOS 180nm process is designed. In the first stage, the capacitive cross coupling dual input structure is used. The design results show that the amplifier can restrain the influence of gold wire bonding. The new rectangular spiral inductor is used in the amplifier, and the area of the chip is reduced to 0.144 mm / 2 compared with that of the single-ended low noise amplifier chip.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN722.3

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