小数分频环形压控振荡器锁相环的研究与设计

发布时间：2018-03-23 23:26

本文选题：锁相环　切入点：环形压控振荡器　出处：《山东大学》2017年硕士论文

【摘要】：锁相环(Phase-Locked Loops,PLL)是现代无线通信系统中的关键模块,它为调制和解调提供本地振荡信号,其性能指标对收发系统的性能指标有较大的影响。此外,在芯片时钟源、时钟提取等电路中,锁相环电路也占有着重要的地位。因此锁相环路一直是研究的热点,它的性能指标:相位噪声、功耗、调谐范围、面积等是主要的关注点。由于消费类电子产品的广泛应用,低功耗、低成本的频率综合器被大量采用。本文针对 ISM(Industrial Scientific Medical Band)频段的 433MHz 无线技术应用需求,完成了一个噪声性能良好、功耗低、成本低的锁相环设计。文章首先对国内外锁相环研究的发展过程和现状做了综述,然后介绍了锁相环的基本电路结构、工作原理、电路模块分类、性能指标等内容,讨论了影响锁相环性能的电路参数。接着采用s域模型对锁相环电路进行噪声分析,推导锁相环的噪声传递函数,并在Matlab中使用Simulink仿真工具搭建功能仿真电路,验证锁相环电路模块的噪声贡献。然后根据应用需求选择了交叉耦合的PMOS环形振荡器、带有MASH1-1-1结构的Delta-Sigma调制器的小数分频器、电流舵低失配电荷泵等电路。论文分析了电路可能产生的温度漂移、电路非理想性等问题,提出了电阻温度补偿的方法和采用低电流失配电路改善温度稳定性的方法。通过选择比较合理的设计参数,完成了对锁相环噪声、功耗、面积的优化。通过版图的绘制技巧减小了锁相环的性能损失,最后对实际流片的芯片进行了板上测试。电路在TSMC0.18μmRFCMOS工艺下实现。最终的结果显示,锁相环在1.8V电源电压下,工作在433.92MHz频点处的相位噪声为-100.36 dBc/Hz@lMHz,功耗约为6.84mW,调谐范围为260MHz-880MHz,满足了设计需求。
[Abstract]:Phase-Locked Loop PLL is a key module in modern wireless communication system. It provides local oscillation signal for modulation and demodulation, and its performance index has great influence on the performance index of transceiver system. Phase locked loop (PLL) plays an important role in clock extraction and other circuits, so PLL is always the focus of research. Its performance indexes include phase noise, power consumption, tuning range, etc. Due to the wide application of consumer electronic products, low power consumption and low cost frequency synthesizers are widely used. This paper aims at the application demand of 433MHz wireless technology in ISM(Industrial Scientific Medical band. A design of PLL with good noise performance, low power consumption and low cost is completed. Firstly, the development process and present situation of PLL research at home and abroad are summarized, and then the basic circuit structure and working principle of PLL are introduced. The circuit parameters which affect the performance of PLL are discussed, and then the noise of PLL circuit is analyzed by using s domain model, and the noise transfer function of PLL is deduced. The Simulink simulation tool is used to build the functional simulation circuit in Matlab to verify the noise contribution of the PLL circuit module. Then the cross-coupled PMOS ring oscillator and the fractional frequency divider of the Delta-Sigma modulator with MASH1-1-1 structure are selected according to the application requirements. The current rudder low mismatch charge pump and other circuits are analyzed in this paper, the possible temperature drift of the circuit, the circuit non-ideal and so on are analyzed. The method of resistor temperature compensation and the method of improving temperature stability by using low current mismatch circuit are put forward. By selecting more reasonable design parameters, the noise and power consumption of phase-locked loop are achieved. Area optimization. The performance loss of PLL is reduced by layout drawing technique. Finally, the chip of real chip is tested on board. The circuit is realized in TSMC0.18 渭 mRFCMOS technology. The final result shows that the PLL is at 1.8V power supply voltage. The phase noise at 433.92MHz frequency is -100.36 dBc / HzlMHz. the power consumption is about 6.84mW, and the tuning range is 260MHz-880MHz, which meets the design requirements.
【学位授予单位】：山东大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.8;TN752

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