高频多路低噪声合成频率源设计与实现

发布时间：2018-03-24 09:16

本文选题：合成频率源　切入点：多路信号输出　出处：《电子科技大学》2017年硕士论文

【摘要】：为了满足自动测试系统中对不同时钟信号的需求,本课题对低噪声频率源关键技术进行了分析,并给出了一种低相位噪声时钟信号的产生方法。在此基础上,设计了一个多路输出的低噪声合成频率源,实现了多个高精度、低噪声的时钟信号输出。本文首先针对低噪声多路输出合成频率源的关键技术进行了分析,包括对各种频率合成方式进行了对比,对锁相式合成频率源的原理及影响噪声的环节进行了分析,对多路信号输出模块及合成频率源的噪声抑制方法进行了研究。然后通过对不同方案的原理进行仿真分析与对比,设计并实现了多路输出的低噪声合成频率源。最后对设计调试过程中的关键难点进行了分析。本文主要内容包括以下几个方面:一、多路信号输出的合成频率源方案设计。频率合成模块是合成频率源的核心部分。本文对多种频率合成方式的特点进行分析和对比,结合实际需求,采用了多路独立锁相环电路加时钟缓冲器的电路结构,实现了目标频率的合成,并通过相互独立的信号调理通道输出,保证了输出信号符合技术指标要求。二、锁相环电路分析及其控制电路设计。对锁相环电路特性进行了分析和仿真,研究了环路滤波器对相位噪声和锁定时间的影响。并给出了频率控制字的写入方法及控制电路。三、输出信号的低噪声设计。分析了影响输出信号相位噪声的各个环节,具体包括信号的产生电路、信号的放大与滤波器电路、供电电源等。对影响输出信号相位噪声的主要电路进行低噪声设计。四、实现了完整的硬件电路,并进行了调试及详细测试。验证了多路信号输出的合成频率源设计方案,总结了调试过程中遇到的问题和解决方法。经过测试验证,所有输出信号频率精度均在0.1ppm以内,输出信号功率及相位噪声指标均满足要求。通过本课题给出的多路输出方案,10MHz输出信号精度达到了0.02ppm以内,输出信号间的延迟达到100ps以内。并通过输出信号的降噪处理,输出信号近旁单边相噪有明显优化。
[Abstract]:In order to meet the requirements of different clock signals in automatic test system, the key technology of low noise frequency source is analyzed in this paper, and a method of producing low phase noise clock signal is given. In this paper, a low noise synthesizing frequency source with multiple outputs is designed, and several clock signals with high precision and low noise are realized. Firstly, the key technology of synthesizing frequency source with low noise output is analyzed in this paper. Including the comparison of various frequency synthesis methods, the principle of phase-locked synthesis frequency source and the influence of noise are analyzed. The noise suppression methods of multi-channel signal output module and synthetic frequency source are studied, and then the principle of different schemes is simulated and compared. A low noise synthesizing frequency source with multiple output is designed and implemented. Finally, the key difficulties in the design and debugging are analyzed. The main contents of this paper are as follows: 1. The design of synthetic frequency source with multi-channel signal output. Frequency synthesis module is the core part of synthetic frequency source. The circuit structure of multi-channel independent phase-locked loop circuit and clock buffer is adopted to realize the synthesis of target frequency, and the output signal of independent signal conditioning channel is ensured that the output signal meets the technical requirements. Phase locked loop circuit analysis and control circuit design. The circuit characteristics of phase locked loop are analyzed and simulated, the influence of loop filter on phase noise and locking time is studied, and the writing method and control circuit of frequency control word are given. The low noise design of output signal is analyzed, including the circuit of signal generation, the circuit of signal amplification and filter, which affect the phase noise of output signal. The main circuits which affect the phase noise of the output signal are designed with low noise. Fourthly, the complete hardware circuit is realized, and the debugging and detailed testing are carried out. The design scheme of the synthetic frequency source of the multi-channel signal output is verified. The problems and solutions in debugging are summarized. The frequency accuracy of all output signals is within 0.1ppm. The output signal power and phase noise index meet the requirements. The output signal accuracy of 10MHz is within 0.02ppm, the delay between output signals is within 100ps, and the noise reduction of output signal is achieved by the de-noising processing of output signal. The one-sided phase noise near the output signal is obviously optimized.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN74

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