ASIC后端设计中的时钟树综合优化研究

发布时间：2018-03-26 11:32

本文选题：物理设计　切入点：低功耗　出处：《湘潭大学》2015年硕士论文

【摘要】：本文针对一款物联网控制的DSP芯片ADP32,在后端物理设计中提出了一种优化的时钟树综合方法。实验数据表明该方法在确保电路时序收敛的前提下有效精简了时钟树结构,减小了时钟树功耗和面积,目前该款芯片已经成功进入流片阶段。时钟信号是电路正常工作的基准,也是电路系统中连线最长、翻转率最高、负载最大的信号。时钟信号必须保证芯片处于最差环境时,最关键的时序也能够正常工作,否则就会导致时序紊乱,电路功能出错。ASIC后端物理设计中的时钟树综合优化是将前端综合时的理想时钟信号换成实际信号连线,也是整个后端设计中十分关键的一步。时钟树综合的目的是最小化时钟延时和偏差,最大限度的获得时序收敛,同时精简时钟缓冲器数目和最小化面积,降低时钟树功耗。总之,一个时钟树的好坏直接影响整个芯片的面积、功耗和布通率。本文是基于Cadence公司的布局布线工具SOC Encounter平台,结合ADP32芯片的后端物理设计流程,展开的时钟树综合优化研究。首先简单介绍了后端设计的基本流程和各个流程阶段的内容及注意事项;然后针对本论文的研究课题时钟树综合优化详细阐述涉及到的基本原理和时钟网络分类;最后通过仔细分析本设计的时钟树结构,结合在实际项目中遇到的问题进行分析并提出解决方案,另外在确保时序收敛的前提下,提出一种通过优化和设置时钟树指导文件中的Buffer、Global Excluded Pin及Leaf Pin Group三个参数综合得到功耗低、面积小时钟树的方法。实验结果表明,这三种参数的合理利用,相比于传统时钟树综合方法,时钟树功耗优化了3.6%,芯片面积减小了0.4%。
[Abstract]:In this paper, an optimized clock tree synthesis method is proposed for ADP32, a DSP chip controlled by the Internet of things. Experimental data show that the proposed method can effectively simplify the clock tree structure while ensuring the convergence of circuit timing. It has reduced the power consumption and area of the clock tree. At present, the chip has successfully entered the stage of the stream chip. The clock signal is the reference for the circuit to work normally, and it is also the longest connection and the highest turnover rate in the circuit system. The most loaded signal. The clock signal must ensure that the chip is in the worst environment, the most critical timing can also work properly, otherwise it will lead to timing disorder, The optimization of clock tree synthesis in the backend physical design of ASIC is to replace the ideal clock signal with the actual signal line. The purpose of clock tree synthesis is to minimize clock delay and deviation, maximize timing convergence, and reduce the number of clock buffers and minimize the area. In a word, the quality of a clock tree directly affects the area, power consumption and routing rate of the whole chip. This paper is based on the layout and wiring tool SOC Encounter platform of Cadence Company, combined with the back-end physical design flow of ADP32 chip. Firstly, the basic flow of the back-end design, the contents of each process and the points for attention are introduced. Then, the basic principle and the classification of clock network are elaborated in detail for the research topic of this thesis. Finally, the clock tree structure of this design is analyzed carefully. Combined with the problems encountered in the actual project to analyze and propose solutions, in addition to ensure the convergence of time series, A method of synthesizing the three parameters of buffer Global Excluded Pin and Leaf Pin Group in the clock-tree guidance file to obtain low power consumption and small area clock tree is proposed. The experimental results show that the three parameters are reasonably utilized. Compared with the traditional clock tree synthesis method, the clock tree power consumption is optimized by 3.6 and the chip area is reduced by 0.4.
【学位授予单位】：湘潭大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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