功率VDMOS器件SPICE模型研究

发布时间：2018-03-26 11:38

本文选题：功率VDMOS器件　切入点：紧凑模型　出处：《东南大学》2015年硕士论文

【摘要】：垂直双扩散金属-氧化物半导体场效应晶体管(VDMOS)由于高输入阻抗、低驱动功率及高开关速度等优势,已广泛应用于各种功率集成电路领域。SPICE器件模型是由SPICE仿真器使用的基于文本描述的模型,是连接器件工艺与电路设计的桥梁。然而,目前业界还没有被广泛认可的功率VDMOS器件SPICE模型,为此,针对功率VDMOS器件SPICE模型的深入研究意义重大。本文系统建立了一套完整的功率VDMOS器件SPICE模型,包括基于表面势的直流特性模型和基于电荷的交流特性模型。直流特性建模时,将器件分为沟道区、积累层电阻区、寄生JFET区、N-外延层区以及N+衬底区5个部分,提出了全新的基于表面势的沟道区模型和积累层电阻模型,进而对寄生JFET区耗尽及夹断两种状态进行分析,建立了寄生JFET区模型,根据外延层区和衬底区的电流路径,建立了N-外延层模型和N+衬底区模型。另外,本文还建立了包括栅源电容Cgs模型、栅漏电容Cgd模型、漏源电容Cds模型在内的交流特性模型。随后,通过Verilog-A语言对上述功率VDMOS器件模型进行描述,运用测试平台获取器件的直流特性数和交流特性数据。最后,根据上述的器件模型和测试数据,进行模型参数提取工作,并给出基于模型仿真数据的验证结果。本文建立的功率VDMOS器件SPCIE模型具有明确的物理意义,模型仿真速度快、收敛性高；验证结果表明,直流特性模型的仿真曲线与测试数据之间的均方根误差均在5%以内,交流特性模型均在7%以内,并能直接应用于SPICE仿真软件,实现了论文的预期目标。
[Abstract]:Vertical double diffusion metal-oxide semiconductor field effect transistor (VDMOS) has the advantages of high input impedance, low driving power and high switching speed. Spice device model is a text-based model used by SPICE simulator and is a bridge between connector process and circuit design. At present, there is no widely recognized SPICE model for power VDMOS devices. Therefore, it is of great significance to study the SPICE model of power VDMOS devices. In this paper, a complete SPICE model of power VDMOS devices is established. It includes DC characteristic model based on surface potential and AC characteristic model based on charge. In DC characteristic modeling, the device is divided into five parts: channel region, accumulative layer resistance region, parasitic JFET region, N-epitaxial layer region and N substrate region. A new channel region model based on surface potential and an accumulative layer resistance model are proposed. The parasitic JFET region depletion and clamping states are analyzed, and the parasitic JFET region model is established according to the current paths in the epitaxial layer and substrate region. N- epitaxial layer model and N substrate model are established. In addition, the AC characteristic models including gate source capacitance Cgs model, gate leakage capacitance Cgd model, drain source capacitance Cds model are also established. The model of the power VDMOS device is described by Verilog-A language, and the DC characteristic number and AC characteristic data of the device are obtained by using the test platform. Finally, according to the above device model and test data, the model parameters are extracted. The power VDMOS device SPCIE model established in this paper has clear physical significance, fast simulation speed and high convergence. The root mean square error between the DC characteristic model and the test data is less than 5%, and the AC characteristic model is less than 7%. It can be directly applied to the SPICE simulation software and achieve the expected goal of the paper.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386

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