基于概率CMOS模型的反馈环路的数字电路容错特性分析

发布时间：2018-03-26 19:04

本文选题：反馈电路　切入点：容错　出处：《电子与信息学报》2017年07期

【摘要】：反馈环路是模拟电路中有效容错的电路结构。反馈电路也因其存储性能而被广泛使用于数字电路的时序电路中,但是反馈电路在数字电路的组合电路的稳定特性鲜少被人研究,尤其是低功耗应用。以马氏随机场为理论的MRF电路以其低功耗下的高稳定性得到研究和关注,但其电路的反馈结构缺乏理论支持和依据,因此马氏随机场电路的容错特性未被清晰得以解释。该文以利用概率CMOS建模概率门来分析MRF核心反馈环NAND-NAND,从理论上证明了反馈电路输出的计算正确概率具有递增且上有界的特点,并数学证明了MRF的核心反馈环电路具有优于传统CMOS电路的容错性能。其理论推导结果与测试结果呈现一致性。
[Abstract]:Feedback loop is an effective fault-tolerant circuit structure in analog circuits. Feedback circuits are also widely used in sequential circuits of digital circuits because of their storage performance, but the stability of feedback circuits in the combination circuits of digital circuits is seldom studied. Especially for low power applications, the MRF circuits based on Markov random field theory have been studied and paid attention to for their high stability under low power consumption, but the feedback structure of the circuits lacks theoretical support and basis. Therefore, the fault-tolerant characteristics of Markov random field circuits have not been explained clearly. In this paper, we use probabilistic CMOS modeling probability gate to analyze the MRF core feedback loop NAND-NAND. it is proved theoretically that the correct calculation probability of feedback circuit output is increasing. And the characteristic of upper bound, It is proved mathematically that the core feedback loop circuit of MRF has better fault-tolerant performance than the traditional CMOS circuit, and the theoretical derivation results are consistent with the test results.
【作者单位】：电子科技大学通信抗干扰国家级重点实验室;
【基金】：国家自然科学基金(61371104)~~
【分类号】：TN79

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