用于高速SerDes接口的编解码及收发电路设计

发布时间：2018-03-29 00:09

本文选题：SerDes接口　切入点：编解码　出处：《电子科技大学》2015年硕士论文

【摘要】：SerDes是一种高速串并转换接口芯片,它在通信领域得到了广泛地应用,如:RapidIO接口技术、InfiniBand接口技术和PCIE接口技术。在发送端,SerDes将多路并行数据转换成高速串行数据。在接收端,SerDes将高速串行数据重新转换成并行数据。本文介绍了SerDes芯片的编解码电路和收发电路。其中编解码电路是数字电路,本文采用FPGA来实现,采用IBM公司关于8b/10b的专利来实现。编码和解码部分分别包括两个8b/10b编码和解码模块,分别用两个低频时钟来控制它们,通过乒乓操作将两个8b/10b编码器的结果发射出去。本文详细介绍了编解码电路的模块划分和设计过程,用Isim软件仿真了编解码电路。收发电路的功能是发送和接收低压差分信号,本文比较了四种高速差分接口,它们是LVPECL差分接口、LVDS差分接口、CML差分接口和VML差分接口。由于VML差分接口有功耗更低、容易集成、结构简单和成本低等特点,本文采用了VML差分接口。发送电路包括预加重电路、并串转换电路和驱动电路。其中并串转换电路的功能是将编码电路和发送电路连在一起,将并行信号转换成串行的CMOS电平信号。发送电路的主要部分是驱动电路,它采用了自偏置的差分放大技术,有效地简化了电路,节省了版图面积。同时,发送电路增加了一个预加重模块,增强了发送端差分信号的强度,从而避免因高频信号衰减而导致的功能错误。接收电路包括串并转换电路、阻抗匹配电路和信号丢失检测电路。其中阻抗匹配电路采用片内电阻实现,节省了版图面积,提高了匹配效率;串并转换电路的功能是将接收电路和解码电路连在一起,将串行的CMOS电平信号转换成并行信号。为了避免差分信号在信道内衰减太厉害而导致解码结果出现乱码,本文设计了信号丢失检测电路,用以检测低压差分信号,当差分信号不满足电平要求时,解码电路将停止工作。编解码电路和收发电路分别用Astro软件和全定制的方式实现了版图,它们都采用了TSMC 0.13 um的CMOS工艺。
[Abstract]:SerDes is a high-speed series-parallel conversion interface chip, which has been widely used in the field of communication. Such as: RapidIO interface technology, InfiniBand interface technology and PCIE interface technology. Multiplex parallel data is converted to high-speed serial data at the sending end Serdes. SerDes reconverts high-speed serial data to parallel data at the receiving end. This paper introduces SerDes chip. Encoding and decoding circuits and transceiver circuits in which the codec circuit is a digital circuit, In this paper, FPGA is used to realize, and IBM patent about 8b/10b is adopted. The coding and decoding part includes two 8b/10b coding and decoding modules, which are controlled by two low-frequency clocks. The results of two 8b/10b encoders are sent out by ping-pong operation. This paper introduces the module partition and design process of the encoding and decoding circuit in detail, and simulates the codec circuit with Isim software. The function of the transceiver circuit is to send and receive low-voltage differential signals. In this paper, four high speed differential interfaces are compared. They are LVPECL differential interface and VML differential interface. Because VML differential interface has the advantages of lower power consumption, easier integration, simple structure and low cost, etc. The VML differential interface is adopted in this paper. The transmission circuit includes preweighting circuit, serial converter circuit and drive circuit. The function of the parallel string conversion circuit is to connect the coding circuit with the transmission circuit. The main part of the transmission circuit is the drive circuit, which adopts the differential amplification technique of self-bias, which simplifies the circuit effectively and saves the layout area. The transmission circuit adds a preemphasis module to enhance the strength of the differential signal at the transmitter, thereby avoiding the functional errors caused by the attenuation of the high frequency signal. Impedance matching circuit and signal loss detection circuit, in which impedance matching circuit is realized by in-chip resistor, which saves layout area and improves matching efficiency, the function of series-parallel conversion circuit is to connect the receiving circuit and the decoding circuit together. The serial CMOS level signal is converted into a parallel signal. In order to avoid the signal attenuation in the channel causing the decoding result to be scrambled, a signal loss detection circuit is designed to detect the low-voltage differential signal. When the differential signal does not meet the requirement of the level, the decoding circuit will stop working. The encoding and decoding circuit and the transceiver circuit are implemented by Astro software and fully customized mode respectively. They all adopt the CMOS technology of TSMC 0.13um.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

【共引文献】