DDR3信号完整性分析及在IMX6电路中的应用

发布时间：2018-03-29 01:35

本文选题：信号完整性分析　切入点：DDR3内存　出处：《华南理工大学》2015年硕士论文

【摘要】：现代电子技术的发展日新月异,从上世纪六十年代开始,集成电路按照摩尔定律发展,每隔18个月可容纳晶体管数目增加-倍,性能也提高一倍。随着性能不断提高,集成电路的内部运行频率越来越高,片外总线频率随之增长。板载信号线的频率不断提高,给电路设计带来许多信号完整性方面的问题,如反射、串扰、振铃现象等。高速电路的信号完整性问题,给电路设计带来许多挑战,传输线长度、阻抗、印制板和芯片封装的不合理设计与选择,都会对高速信号造成影响,使信号中出现噪声,进而导致信号失真。文中针对DDR3设计中存在的,拐角阻抗突变、过孔容性负载、延迟线和元器件封装等影响DDR3信号完整性问题进行分析,并提出改进方案。DDR3不同的布线拓扑结构有不同效果,并应用在不同场合和信号频率。文中详细的介绍和分析DDR3布线的各种拓扑结构,特别是T型拓扑、菊花链拓扑和Fly-by拓扑。这三种拓扑都是针对地址/时钟/控制信号的走线拓扑,在1GHz信号频率情况下三种拓扑结构的优缺点并不十分明显。文中分别根据拓扑结构的特点和应用环境,建设性的提出了三种拓扑结构应该在什么条件下使用,使DDR3在不同条件下使用最合适的拓扑结构,优化DDR3信号性能。论文中的电路设计方法引入信号完整性仿真手段。与传统电路设计方法不同,高速电路设计很难根据经验判断信号的好坏,需要结合必要的信号完整性分析方法和仿真手段完成电路设计。在PCB布线阶段对电路信号进行仿真分析,直到信号仿真结果达到要求才进行下一步生产。高速电路的设计方法,不但解决信号完整性问题,还能缩短电子设备的设计周期,有效的保障硬件设计的质量和提高生产效率。课题研究在飞思卡尔处理器IMX6电路中DDR3的运行情况,探讨DDR3电路设计中遇到的信号完整性问题。通过分析对比DDR3不同的拓扑结构,提出各拓扑结构的应用场合,使用仿真手段优化DDR3拓扑结构和布线方案,提高DDR3的性能和稳定性。
[Abstract]:With the rapid development of modern electronic technology, since the 1960s, integrated circuits have been developed in accordance with Moore's law, and the number of transistors can be increased and their performance doubled every 18 months. The frequency of off-chip bus increases with the increasing internal frequency of integrated circuits. The frequency of on-board signal lines is increasing constantly, which brings many problems of signal integrity to the circuit design, such as reflection, crosstalk, etc. The problem of signal integrity of high speed circuit brings many challenges to the circuit design, such as the length of transmission line, impedance, improper design and selection of printed circuit board and chip package, all of which will affect the high speed signal. In this paper, the problems of corner impedance mutation, perforation load, delay line and component package affecting the integrity of DDR3 signal are analyzed. The improved scheme. DDR3 has different effects and is used in different occasions and signal frequencies. The paper introduces and analyzes the various topological structures of DDR3 routing, especially T-type topology. Chrysanthemum chain topology and Fly-by topology. These three topologies are routing topologies for address / clock / control signals, The merits and demerits of the three topologies are not obvious in the case of 1GHz signal frequency. According to the characteristics of the topology and the application environment, this paper constructively proposes the conditions under which the three topologies should be used. Make DDR3 use the most suitable topology under different conditions, and optimize the performance of DDR3 signal. The circuit design method in this paper introduces signal integrity simulation method, which is different from the traditional circuit design method. It is difficult to judge whether the signal is good or bad according to the experience in high-speed circuit design. It is necessary to combine the necessary signal integrity analysis method and simulation method to complete the circuit design. The circuit signal is simulated and analyzed in the stage of PCB wiring. The design method of high-speed circuit not only solves the problem of signal integrity, but also shortens the design period of electronic equipment. This paper studies the operation of DDR3 in IMX6 circuit of Freescale processor, discusses the problem of signal integrity encountered in the design of DDR3 circuit, and analyzes and compares the different topology of DDR3. In order to improve the performance and stability of DDR3, it is proposed that the topology and routing scheme of DDR3 can be optimized by simulation in the applications of various topologies.
【学位授予单位】：华南理工大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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