具有局部重构功能单元的ASIP设计

发布时间：2018-03-29 22:16

本文选题：局部可重构　切入点：ASIP　出处：《西安电子科技大学》2015年硕士论文

【摘要】：随着科学技术的不断发展,以数据密集型应用为代表的数据处理需求越来越复杂,而传统的系统设计方法多采用通用处理器或专用集成电路(ASIC),通用处理器具有性能上的局限性,ASIC虽然能够提供较高的性能,但是其结构决定了它制造完成之后无法进行修改,灵活性不足,设计成本偏高。具有可重构功能单元的ASIP,具有良好的灵活性和较高得性能,能够实现FPGA内部逻辑资源的分时复用,使内部资源得到最大限度的使用。动态局部重构技术,能够在系统正常工作的情况下,实现重构区域内逻辑的重新配置,在线修改动态模块的功能,具有节约硬件资源和增强系统灵活性的优势。本文选择Xilinx Virtex-6 XC6VSX315T芯片,在搭建的系统平台上实现了具有重构功能单元的ASIP设计,实现了对反正切运算和求模运算的局部重构工作。本文主要完成的研究工作包括:(1)讨论了该课题的研究背景和意义,建立了一个可靠的局部重构设计流程,包括对电路功能的Verilog HDL描述,静态区域与动态区域的设计,配置实现与配置文件验证等步骤;(2)结合CORDIC理论方法,使用流水线设计方式,设计了反正切运算的具体电路,能够通过移位和加减法运算实现反正切运算,且误差在系统允许范围内;(3)实现了具有重构功能单元的ASIP的设计,能够根据指令集要求,实现基本运算,并且能够实现反正切运算和平方根运算的重构。对系统进行了仿真实验,实验证明,系统能够实现硬件资源的分时复用,提高了逻辑资源的利用率。
[Abstract]:With the development of science and technology, the demand of data processing, represented by data-intensive applications, is becoming more and more complex. However, the traditional system design methods usually use general purpose processor or ASIC. Although the general purpose processor has the limitation of performance, although it can provide higher performance, its structure determines that it can not be modified after the completion of manufacture. Because of the lack of flexibility and high design cost, the FPGA with reconfigurable function unit has good flexibility and high performance, and can realize the time-sharing reuse of the internal logic resources of FPGA. The dynamic local reconfiguration technology can reconfigure the logic in the reconfigurable region and modify the function of the dynamic module online when the system works normally. It has the advantages of saving hardware resources and enhancing the flexibility of the system. In this paper, the Xilinx Virtex-6 XC6VSX315T chip is selected, and the ASIP design with reconfigurable function unit is realized on the system platform. The main research work in this paper includes: 1) the research background and significance of this subject are discussed, and a reliable local reconstruction design flow is established. Including the Verilog HDL description of circuit functions, the design of static and dynamic regions, configuration implementation and configuration file verification, etc.) combining with CORDIC theory and method, using pipeline design method, designed the specific circuit of the operation. The design of ASIP with reconfigurable function unit can be realized by shift and addition and subtraction operation, and the error is within the allowable range of the system. The basic operation can be realized according to the requirement of instruction set. The simulation results show that the system can realize the time-sharing reuse of hardware resources and improve the utilization of logic resources.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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