基于FPGA的TIADC宽带信号硬件实时修正方法研究

发布时间：2018-04-01 02:26

本文选题：波形数字化　切入点：并行交替采样　出处：《中国科学技术大学》2017年博士论文

【摘要】：在传统物理试验中,发展出了一系列的方法来测量探测器输出信号的电荷和时间信息,然而这些参数只能表征有限的信号特征。若可以获取信号的原始波形,则通过波形分析可以得到信号中包含的所有物理信息。因此波形数字化是物理学家一直以来梦寐以求的目标,也是物理实验电子学领域的一个研究热点。随着高速模拟-数字变换(Analog-to-Digital Conversion,ADC)技术的发展,ADC的采样率越来越高,但是在一些特殊的应用中,仍不能满足我们对波形数字化采样率的要求。如此一来,并行交替采样(Time-Interleaved A/D Conversion,TIADC)技术的出现和发展,不仅在提高单个ADC芯片采样率的设计中得以发挥巨大的促进作用,同时也使得我们可以利用采样率有限的ADC芯片实现更高等效采样速度的波形数字化系统。然而,并行交替采样技术中多个并行采样通道间的失配(增益、时钟相位和直流偏置)是制约TIADC性能提升的主要瓶颈,因此必须解决失配误差带来的性能影响,才能保证TIADC系统本身的实用性。因此TIADC失配误差的修正技术就是一个重要的研究方向。在传统的完美重构修正技术中,可以实现窄带输入信号情况下失配误差的有效修正,然而在实际物理实验中探测器输出信号往往是宽带信号,因此有必要发展一种适合宽带信号下的修正方法,这就是本论文主要的研究方向,同时本论文还着重研究了上述算法的实时硬件实现,并集成在单个FPGA(Field-Programmable Gate Array)芯片中。本论文的第一章介绍了波形数字化技术的基本概念,并简要回顾了其中两个具体的实现技术,包括开关电容阵列和高速ADC,并特别介绍了高速、高精度ADC集成电路技术当前的最新发展水平和技术方向。第二章介绍了 ADC的基本原理和特征参数,并对并行交替采样技术的原理和遇到的技术挑战进行了介绍,同时还回顾了了现有的两大类TIADC系统中通道间失配误差修正方法,一类是基于硬件自适应反馈调节或者软件自适应修正的后台修正技术,另一类是基于前景校准的数字修正技术。第三章中进行了宽带输入信号情况下通道间失配误差修正方法的理论推导,并介绍了其并行化的实现结构,还对修正方法的可行性基于MATLAB平台进行了仿真。进一步地基于此修正方法的特点,对当前常用的FPGA内部DSP(Digital Signal Processing)结构进行了简要的分析,为硬件具体的设计与实现提供了参考。第四章介绍了一 12位8 Gsps TIADC系统的硬件的设计方案。此TIADC系统主要用于上述修正算法正确性和所能达到性能的验证测试。设计中使用2片12位4 Gsps(sample per second,每秒采样次数)的ADC芯片,基于并行交替采样技术实现等效8 Gsps的采样速度,并将所有的修正算法集成在一片FPGA芯片中。第五章介绍了此TIADC硬件系统的具体实现,并详细介绍了 FPGA逻辑的具体设计方案,其中重点介绍了并行修正算法的具体结构。第六章给出了硬件系统的测试结果。测试表明,在1.5GHz宽带范围内,修正后TIADC系统在550 MHz以下有效位好于8.7 Bits,在550 MHz～1500 MHz之间有效位好于8 Bits,基本达到ADC单芯片的性能水平,与其手册中性能指标参数基本相当。此结果表明此修正算法可以明显抑制通道间失配误差的影响。最后一章对论文工作进行总结,并展望下一步工作。
[Abstract]:In the traditional physics experiment, developed a series of methods to measure the charge and time information of the output signal of the detector, but these parameters can only characterize the limited signal characteristics. If the original waveform signal can be obtained, through the waveform analysis can get all the physical information of the signal waveform. Therefore digital physicists have always dreamed of the target, it is also a research focus of physics experiment electronics field. With the high-speed analog to digital converter (Analog-to-Digital Conversion ADC) technology, the sampling rate of ADC is more and more high, but in some special application, we still can not meet the requirements of digital waveform sampling rate. Thus, the parallel alternating sampling (Time-Interleaved A/D Conversion, TIADC) technology emergence and development, not only in a single ADC chip design to improve the sampling rate of Play a huge role in promoting, but also allows us to use sampling digital waveform system ADC chip rate limited to achieve higher equivalent sampling speed. However, the parallel alternating sampling technology of multiple parallel sampling channel mismatches (gain, clock phase and DC bias) is a major bottleneck in improving the performance of TIADC. It must address the effects of mismatch errors caused by the performance, in order to ensure the practicality of the TIADC system itself. Therefore TIADC mismatch error correction technology is an important research direction. In the perfect reconstruction of the traditional correction technique, can achieve narrowband input signal circumstances effectively mismatch correction, however, in the actual physical detector the output signal is the broadband signal, so it is necessary to develop a suitable correction method of the wideband signal, which is the main research direction, at the same time Real-time hardware implementation of this paper also focuses on the above algorithm, and integrated in a single FPGA (Field-Programmable Gate Array) chip. In the first chapter of this thesis introduces the basic concepts of digital waveform technology, and briefly reviews the two specific implementation techniques, including switching capacitor array and high speed ADC, and especially introduces the high speed, high precision ADC integrated circuit technology the latest development level and technical direction. The second chapter introduces the basic principle and characteristic parameters of ADC, and the principle of parallel alternating sampling technology and some technical challenges are introduced, and also reviews the channel two kinds of existing TIADC system in lost with error correction method, a kind of hardware or software adaptive feedback correction technique based on adaptive background correction, the other is the prospect of calibration of digital correction technique based on the third chapter. In the case of broadband signal input channel mismatch theory error correction method, and introduces its parallel implementation structure, but also the feasibility of correction method based on the MATLAB platform simulation. Further on this foundation characteristics of correction method, the current commonly used FPGA DSP (Digital Signal Processing) the structure was briefly analyzed, providing reference for the design and implementation of the hardware. The fourth chapter introduces the design of a 12 bit 8 Gsps TIADC system hardware. This TIADC system is mainly used in the algorithm is correct and can achieve the performance verification test. Using 2 pieces of 12 Gsps design (4 sample per second, the number of samples per second) of the ADC chip, the parallel sampling speed alternating sampling technique to achieve equivalent 8 based on Gsps, and the modified algorithm all integrated in a FPGA chip. The fifth chapter introduces The implementation of the TIADC hardware system, and introduces the concrete design of FPGA logic, which focuses on the specific structure of parallel correction algorithm. The sixth chapter gives the hardware test results. The test shows that the bandwidth of 1.5GHz, the modified TIADC system under 550 MHz effective bit better than 8.7 Bits, from 550 MHz to 1500 MHz between the effective bit better than 8 Bits, the level of performance reached the ADC single chip, and manual performance parameters. The results show that the equivalent correction algorithm can significantly inhibit the effect of channel mismatch error. The last chapter is the summary of the work, and looking forward to the next further work.

【学位授予单位】：中国科学技术大学
【学位级别】：博士
【学位授予年份】：2017
【分类号】：TN792

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