温度与误码率敏感的3D IC测试与DVFS技术研究

发布时间：2018-04-01 07:33

本文选题：3D　切入点：Cache　出处：《合肥工业大学》2015年硕士论文

【摘要】：过硅通孔技术,提供了高密度、低延时和低功耗的垂直互连,芯片在三维方向堆叠的密度大、互连线短,从而使三维堆叠芯片成为可能。凭借单位面积的高存储容量和垂直方向的低延迟优势,三维(3D,Three-Dimensional)存储器堆叠技术已经成为解决2D集成电路(ICs,Integrated Circuits)中芯片内部存储器容量不足和带宽限制问题的最有效方法之一。然而,3D IC高集成度带来的高功耗密度问题大幅提高了芯片内部的工作温度,可能会带来热斑(Hot Spot)问题。显然,高热量问题又会降低芯片的可靠性、增加芯片的故障率、限制3D芯片性能的发挥。针对高温所产生的高故障率,一种被动的方法是对超大规模集成电路进行测试。文章介绍了基于TSVs的三维堆叠芯片新的测试流程、TSVs绑定前测试的挑战和TSVs绑定后的可靠性与测试挑战,重点包括KGD与KGD晶圆级测试和老化、DFT技术、绑定前可测性、测试经济性、TSVs绑定后的可靠性和测试问题,以及三维集成独有的问题,并介绍了这一领域的早期研究成果。另一种更可取的方法,则是在芯片设计之初,主动考虑高温和故障率高的问题。针对含三维堆叠高速缓冲存储器(3D Stacked Caches)芯片,本文提出了一种温度和错误率感知的动态电压和频率缩放(DVFS,Dynamic Voltage and Frequency Scaling)方法(TERA-DVFS,Temperature and Error Rate-Aware DVFS)。实验结果表明,TERA-DVFS能够在3D cache温度和错误率的约束下,以较小的功耗开销,取得较大的性能。
[Abstract]:Through through silicon technology, provides high density, low delay and low power consumption vertical interconnection, chips stacked in the three-dimensional direction of high density, interconnection lines are short, This makes it possible to stack chips in three dimensions. With high storage capacity per unit area and low latency in the vertical direction, Three-dimensional 3D memory stacking technology has become one of the most effective methods to solve the problem of insufficient memory capacity and bandwidth limitation in 2D integrated IC integrated circuits. However, the high integration of 3D IC brings about a large problem of high power density. The amplitude increases the working temperature inside the chip, It can lead to hot spot problems. Obviously, high heat problems can reduce the reliability of chips, increase the failure rate of chips, and limit the performance of 3D chips. A passive method is to test VLSI. This paper introduces the new testing flow of 3D stacked chip based on TSVs and the challenges of TSVs pre-binding test and reliability and test challenge after TSVs binding. The emphasis includes KGD and KGD wafer level testing and aging DFT technology, the testability before binding, the reliability and test problems after testing KGD bindings, and the unique problems of 3D integration. This paper also introduces the early research achievements in this field. Another preferred method is to consider the problems of high temperature and high failure rate at the beginning of chip design. In this paper, a temperature and error rate sensing dynamic voltage and frequency scaling Voltage Voltage and Frequency scaling method is proposed. The experimental results show that TERA-DVFS can achieve better performance under the constraints of 3D cache temperature and error rate.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407

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