基于FPGA的DDR3协议解析逻辑设计

发布时间：2018-04-04 01:03

  本文选题：现场可编程门阵列　切入点：固态盘　出处：《计算机应用》2017年05期

【摘要】：针对采用DDR3接口来设计的新一代闪存固态盘(SSD)需要完成与内存控制器进行通信与交互的特点,提出了基于现场可编程门阵列(FPGA)的DDR3协议解析逻辑方案。首先,介绍了DDR3内存工作原理,理解内存控制器对存储设备的控制机制;然后,设计了接口协议解析逻辑的总体架构,采用FPGA实现并对其中的各个关键技术点,包括时钟、写平衡、延迟控制、接口同步控制等进行详细阐述;最后,通过modelsim仿真并进行板级验证,证明了该设计的正确性和可行性。在性能方面,通过单次读写、连续读写和混合读写三种模式下的数据读写测试,取得了最高77.81%的DDR3接口带宽利用率,在实际的SSD开发过程中能够有效提高系统的访问性能。
[Abstract]:Aiming at the need to communicate and interact with the memory controller, a new generation of flash memory solid-state disk (SSDs) designed with DDR3 interface is proposed. A DDR3 protocol parsing logic scheme based on FPGA (Field Programmable Gate Array) is proposed.First of all, the principle of DDR3 memory is introduced, and the control mechanism of memory controller to storage device is understood. Then, the architecture of interface protocol parsing logic is designed, which is implemented by FPGA and every key technology, including clock, is implemented.Write balance, delay control and interface synchronization control are described in detail. Finally, the correctness and feasibility of the design are proved by modelsim simulation and board level verification.In terms of performance, the data read and write tests in single read / write mode, continuous read / write mode and mixed read / write mode are carried out, and the maximum bandwidth utilization of DDR3 interface is 77.81%, which can effectively improve the access performance of the system in the actual SSD development process.
【作者单位】： 国防科学技术大学计算机学院;高性能计算国家重点实验室(国防科学技术大学);
【基金】：国家自然科学基金资助项目(NSFC61433019,NSFC61472432)~~
【分类号】：TN791;TP333
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本文编号：1707690