纳米集成电路软错误评估方法研究

发布时间：2018-04-07 15:00

本文选题：扇出重汇聚　切入点：负偏置温度不稳定性　出处：《合肥工业大学》2015年博士论文

【摘要】：随着集成电路工艺水平的不断进步,芯片集成度和性能大幅提升,而其面积和供电电压却不断减小。但是,工艺尺寸的不断缩减对集成电路的可靠性也带来巨大挑战。纳米工艺下,软错误是导致集成电路发生失效的重要因素。同时,负偏置温度不稳定性(NBTI)和传播导致的脉冲展宽(PIPB)、考虑多时钟周期的故障脉冲叠加等情形进一步加重了集成电路失效。已有数据表明,组合逻辑发生软错误的比重已与存储器电路相当,并且在已工作10年的最坏情况下,软错误率(SER)和电路延迟均有近20%的增加,导致电路更容易出现功能失效。为了准确评价不同电路对软错误的敏感程度,并为电路的选择性加固提供依据,本论文针对纳米集成电路软错误评估技术进行研究,分别基于输入向量、故障概率方法,并从协同考虑NBTI和PIPB导致故障脉冲的展宽、考虑多时钟周期故障脉冲叠加的角度对软错误评估方法进行阐述,主要研究内容和创新点如下：(1)考虑扇出重汇聚的集成电路软错误率评估。针对考虑扇出重汇聚的软错误评估问题,基于输入向量方法,提出一种考虑扇出重汇聚的电路软错误率评估方法。通过门级仿真和故障注入,使用提出的考虑扇出重汇聚的敏化路径逼近搜索算法计算逻辑门到锁存器的敏化路径和管脚延迟；分别将不同有效宽度的单粒子瞬态(SET)故障脉冲在敏化路径上传播,并使用脉冲屏蔽模型评估电气屏蔽和时窗屏蔽效应；最后使用提出的软错误率评估方法计算可得电路总体软错误率。实验结果表明,由于考虑扇出重汇聚的影响,进一步提高了软错误率评估的准确度。(2)考虑NBTI效应的集成电路软错误率评估。针对SET脉冲在产生和传播过程中发生展宽的问题,提出一种考虑NBTI效应的集成电路软错误率评估方法。基于SET脉冲在产生过程中展宽的解析模型对初始SET脉冲进行展宽,使用NBTI模型计算P沟道金属氧化物半导体(PMOS)晶体管阈值电压增量并映射到工艺预测模型(PTM)卡；使用考虑老化的集成电路模拟程序(HSPICE)测量SET脉冲在门单元中传播时的展宽,并同时考虑PIPB效应；最终将传播到锁存器的SET脉冲进行软错误率计算。实验结果表明,提出的方法能够准确评估集成电路在其生命周期各个阶段的软错误率,并在设计阶段为电路的选择性加固提供参考。(3)考虑多时钟周期故障脉冲叠加的锁存窗屏蔽模型。针对故障脉冲的叠加,以及叠加的故障脉冲在多个时钟周期内对锁存器采样的干扰问题,提出一种考虑多时钟周期故障脉冲叠加的锁存窗屏蔽模型。先计算考虑扇出重汇聚的敏化路径和管脚延迟；然后在扇出重汇聚路径上使用脉冲叠加计算方法对脉冲进行叠加；最后对传播到锁存器的脉冲进行软错误率计算。实验结果表明,提出的方法与不考虑多时钟周期故障脉冲叠加的方法相比,在可容忍的时间开销内,平均提高7.5%的软错误率评估准确度。(4)基于故障概率的集成电路软错误率评估。针对输入向量空间的不完备性,以及输入向量方法的评估速度较慢的问题,提出一种基于故障概率的集成电路软错误率评估方法。使用门级仿真器获得各个逻辑门输出端信号概率,将信号概率值进行反转以模拟故障注入,使用数据路径检索算法查找故障门到锁存器的数据路径；在数据路径上使用SET故障脉冲模拟粒子撞击,使用提出的软错误率评估方法计算可得电路总体软错误率。实验结果表明,与基于输入向量的方法相比,在等效精度下,文中方法平均提高近200倍的软错误率评估速度。
[Abstract]:With the development of integrated circuit technology, the chip integration and performance significantly improved, and the area and power supply voltage has been reduced. However, the process dimension shrinking reliability of integrated circuit is also a huge challenge. The nano technology, soft error is an important factor in integrated circuit failure. At the same time, negative bias temperature instability (NBTI) and pulse broadening caused by propagation (PIPB), considering the multi cycle pulse superimposed fault situation further aggravated by the failure of the integrated circuit. The existing data show that the proportion of occurrence of soft errors in combinational logic and memory circuits, and in the worst case has been working for 10 years, soft the error rate (SER) and increase the circuit delay has nearly 20%, the circuit is more prone to failure. In order to accurately evaluate the sensitivity of different circuit soft error, and selective circuit This thesis aims to provide the basis for reinforcement, nano integrated circuit soft error evaluation technology research, based on the input vector respectively, fault probability method, and from NBTI and PIPB to consider collaborative fault pulse broadening, multiple clock cycle fault pulse superposition of soft error evaluation methods are presented in this paper, the main research contents and innovations are as follows: (1) consider reconvergent fanout integrated circuit soft error rate evaluation. According to the evaluation problem of soft error reconvergent fanout, input vector based method, put forward an evaluation circuit soft error rate consider reconvergent fanout method. Through the gate level simulation and fault injection, sensitization path using the proposed considering reconvergent fanout the approximate search algorithm to compute logic gates to sensitized path latch and pin delay; single particle transient respectively different effective width (SET) pulse in sensitized fault On the path of propagation, and the use of pulse shielding model evaluation of electrical shielding and window shielding effect; finally put forward the evaluation method using a soft error rate can be calculated overall circuit soft error rate. The experimental results show that, because of considering the influence of reconvergent fanout, further improve the soft error rate evaluation accuracy (2) is considered. Evaluation of soft error rate of integrated circuit NBTI effect. For the SET pulse broadening occurs in the generation and propagation process, proposes a soft error rate evaluation of integrated circuit with NBTI effect method. SET pulse broadening in the analytical model in the process of initial SET pulse broadening calculation based on P channel metal oxide semiconductor using the NBTI model (PMOS) transistor threshold voltage increment and mapped to the process model (PTM); using the simulation program considering the integrated circuit aging (HSPICE) measurement of SET pulse in door unit Broadening of the propagation, and considering the PIPB effect; will eventually spread to latch the SET pulse soft error rate is calculated. The experimental results show that the proposed method can accurately evaluate the integrated circuit soft error in the life cycle of each stage, and in the design stage for selective circuit reinforcement for reference. (3) consider the window latch shielding model clock cycle fault pulse superposition. According to superposition of fault pulse, and the pulse superposition fault in multiple clock cycles to latch the interference sampler, a latch window shield model clock cycle fault pulse superposition consideration. First calculate the tube the foot and sensitizable path delays reconvergent fanout; then reconvergent fanout path calculation method using pulse superposition superposition of pulses; finally the pulse spread to latch the soft error rate calculation. The experimental results show that the proposed method and does not consider the method of multi clock cycle fault pulse superposition compared with tolerable time, an average increase of 7.5% soft error rate estimation accuracy. (4) to evaluate the rate of soft errors in integrated circuit based on fault probability. The input space is not complete, and evaluation of slow input vector method, put forward a kind of integrated circuit soft error rate estimation based on fault probability method. Using the gate level simulator for each logic gate output signal probability, the signal probability value to simulate the fault injection inversion, using the data path search algorithm to find the fault door to the data path of the latch; SET fault simulation using pulse particle impact on the data path, using the evaluation method of the soft error rate can be calculated overall circuit soft error rate. The experimental results show that based on the transmission and Compared with the method of entering the vector, under the equivalent precision, the method in the paper improves the speed of the soft error rate assessment by nearly 200 times.

【学位授予单位】：合肥工业大学
【学位级别】：博士
【学位授予年份】：2015
【分类号】：TN40

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