硅基毫米波低噪声放大器和混频器的研究与设计

发布时间：2018-04-09 02:03

本文选题：毫米波　切入点：CMOS工艺　出处：《杭州电子科技大学》2017年硕士论文

【摘要】：随着无线通讯技术的迅猛发展,用户对大数据吞吐量的通信系统的需求日益强烈。大数据吞吐量意味着高的传输速率,根据Shannon定理可知,随着系统传输速率的提高,系统传输带宽也要相应的变宽。毫米波频段具有丰富的频谱资源,可用带宽大、可使用的频谱资源广。因此,毫米波频段通信系统的研究越来越受到国内外研究人员的青睐。同时,伴随着硅基工艺的快速发展,硅基集成电路工艺特征尺寸不断减小,硅基有源器件的截止频率fT和最大震荡频率fmax逐步进入了太赫兹频段,为硅基毫米波乃至太赫兹频段通信系统及其相关电路的研究奠定了工艺基础。本文基于CMOS工艺,以毫米波接收机前端电路:低噪声放大器(LNA)和混频器(Mixer)为主要对象进行研究与设计。本文开头介绍了硅基毫米波电路的研究现状,分析了几种常见的接收机结构以及接收机前端低噪声放大器和混频器的相关理论。通过调查与研究,确定了60GHz和280GHz硅基毫米波接收机架构,并对其进行了链路建模和仿真。文中深入讨论了60GHz宽带低噪声放大器的设计及工作频率超过器件截止频率的280GHz混频器的设计。主要研究内容和贡献如下:(1)对60GHz和280GHz零中频接收机架构进行了链路建模和仿真,验证了该接收机架构的可行性,确定了接收机各模块的性能指标,为后续设计60GHz宽带低噪声放大器和280GHz混频器提供了设计依据。(2)为了满足宽带系统的需求,本文提出了一款用于60GHz接收机的宽带低噪声放大器电路结构,在不恶化电路噪声和放大器增益的同时实现了宽带性能。该低噪声放大器基于SMIC 40nm CMOS工艺,采用了三级级联结构。第一级采用具有负反馈的共源共栅电路结构实现宽带和噪声消除;第二、三级采用电容交叉耦合中和技术,实现高增益和高隔离度;级间采用无源变压器,实现级间耦合、直流供电和拓展带宽。后仿真结果表明该低噪声放大器在60GHz时的增益为21dB,最优噪声系数为6.16dB,IIP3为-8.95dBm。3dB带宽为25GHz(45~70GHz),在整个带宽范围内增益平坦,噪声系数小于7.75dB。(3)针对工作频率超过有源器件截止频率的280GHz接收机架构,本文着重研究了无源混频器,并基于Global Foundries 65nm CMOS工艺,设计了一款无源SubHarmonic混频器。后仿真结果表明,该混频器的中频3dB带宽为5GHz,转换损耗为24.8dB~27.5dB,噪声系数小于24.76dB。在中频输出为4GHz时,噪声系数最小,为20.13dB。与当前的研究对比,本文所设计的混频器在转换损耗可比拟的情况下,具有最低的噪声系数。
[Abstract]:With the rapid development of wireless communication technology, users' demand for big data's throughput communication system is increasing.Big data's throughput means high transmission rate. According to Shannon theorem, with the increase of transmission rate, the system bandwidth should be widened accordingly.Millimeter wave frequency band has rich spectrum resources, the available bandwidth is large, and the spectrum resources can be used widely.Therefore, the research of millimeter wave communication system is more and more popular at home and abroad.At the same time, with the rapid development of silicon based technology, the characteristic size of silicon based integrated circuit process is decreasing, and the cutoff frequency fT and the maximum oscillation frequency fmax of silicon based active devices are gradually entering terahertz band.It lays a technological foundation for the study of silicon-based millimeter wave and even terahertz communication system and its related circuits.Based on CMOS technology, this paper studies and designs the front-end circuits of millimeter-wave receiver: low noise amplifier (LNA) and mixer Mixer.At the beginning of this paper, the research status of silicon-based millimeter-wave circuits is introduced, and several common receiver structures are analyzed, as well as the theory of receiver front-end low-noise amplifier and mixer.Through investigation and research, the architecture of 60GHz and 280GHz silicon-based millimeter wave receiver is determined, and its link modeling and simulation are carried out.The design of 60GHz wideband low noise amplifier and the design of 280GHz mixer whose operating frequency exceeds the cutoff frequency of the device are discussed in detail.The main research contents and contributions are as follows: (1) Link modeling and simulation of 60GHz and 280GHz zero-if receiver architecture are carried out, the feasibility of the receiver architecture is verified, and the performance index of each module of the receiver is determined.In order to meet the requirements of broadband system, a broadband low noise amplifier (LNA) structure for 60GHz receiver is proposed in this paper, which provides a design basis for the subsequent design of 60GHz LNA and 280GHz Mixer) in order to meet the requirements of wideband system, this paper proposes a broadband LNA circuit structure for 60GHz receiver.Wideband performance is achieved without worsening circuit noise and amplifier gain.The low noise amplifier is based on the SMIC 40nm CMOS process and adopts a three-stage cascade structure.In the first stage, the common grid circuit structure with negative feedback is used to realize wideband and noise elimination; in the third stage, the capacitive cross-coupling neutralization technique is used to achieve high gain and high isolation; and the passive transformer is used among the stages to realize the interstage coupling.DC power supply and bandwidth expansion.The simulation results show that the gain of the LNA is 21dB at 60GHz, and the optimal noise coefficient is 6.16dBNIIP3. The bandwidth of the LNA is -8.95dBm.3dB and the bandwidth is 25GHz / 4570GHz, and the gain is flat in the whole bandwidth range.Aiming at the architecture of 280GHz receiver whose operating frequency exceeds the cut-off frequency of active devices, the passive mixer is studied in this paper. Based on the Global Foundries 65nm CMOS technology, a passive SubHarmonic mixer is designed.The simulation results show that the if 3dB bandwidth of the mixer is 5GHz, the conversion loss is 24.8dBU 27.5dB, and the noise coefficient is less than 24.76dB.When the intermediate frequency output is 4GHz, the noise coefficient is the smallest, 20.13 dB.Compared with the current research, the mixer designed in this paper has the lowest noise coefficient under the condition that the conversion loss is comparable.
【学位授予单位】：杭州电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN722.3;TN773

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