一种低压高速的流水线型ADC数字校正系统的研究与实现

发布时间：2018-04-09 20:10

本文选题：流水线型ADC　切入点：失配误差校正　出处：《电子科技大学》2015年硕士论文

【摘要】：现代社会正处于一个数字信息飞速膨胀的时代,将连续的模拟信号转化为数字信号的接口模拟-数字转换器(ADC)应用越来越广泛,复杂的应用场合对ADC性能的要求也日益提高。流水线型ADC凭借其可实现的中高速速度和中高精度分辨率,在中高速ADC应用场合使用最普遍,同时也最受广大学者和工程师的青睐。鉴于流水线型ADC功耗较大的劣势和采样保持电路消耗功率最大的特点,设计无采保的流水线型ADC已成为ADC高速低功耗应用中的迫切需求。首先,本文从流水线型ADC工作的基本原理入手,建立了流水线型ADC的数学模型,并详细分析了ADC中存在的各种误差源和相应的影响。运用Matlab软件,对一种10位500 MSPS无采保的流水线型ADC进行了行为级建模,针对级电路中存在的电容失配误差和增益误差,提出了前台校正技术和后台校正技术相结合的数字校正算法,并进行了行为级验证。行为级仿真结果显示,校正算法能够有效地提升流水线型ADC的动态范围和噪声性能,有效精度可以提升大约3Bits。然后,本文运用VHDL硬件语言,将已经通过行为级验证的校正算法,转换成可综合的RTL(寄存器)级数字电路,并运用Modelsim软件对代码进行了仿真和验证。仿真结果显示,所有的待校正的误差均存在校正过程,并且最终的校正值在合理范围之内。最后,基于0.13μm标准CMOS工艺,依据数字集成电路设计的流程,运用Design Complier和Encounter等EDA设计工具,将校正算法转换为物理可实现的数字版图,并且进行了后仿真验证。最终获得的数字版图面积为800μm*600μm,后仿真结果也符合预期的结果。
[Abstract]:The modern society is in the era of rapid expansion of digital information. The continuous analog signal is converted into the interface of digital signal. ADCC is more and more widely used, and the demand for ADC performance in complex applications is also increasing day by day.Pipeline type ADC is widely used in ADC applications because of its medium and high speed speed and high resolution. At the same time, it is favored by many scholars and engineers.In view of the disadvantages of pipeline type ADC and the maximum power consumption of the sampling and holding circuit, it has become an urgent demand in the application of ADC high speed and low power to design the ADC with no sampling and protection.Firstly, this paper starts with the basic principle of pipeline type ADC, establishes the mathematical model of pipeline type ADC, and analyzes in detail all kinds of error sources and corresponding influences in ADC.Using Matlab software, the behavioral model of pipeline type ADC with 10 bits 500 MSPS is built. The capacitance mismatch error and gain error in the stage circuit are analyzed.A digital correction algorithm combining foreground correction and background correction is proposed, and the behavior level verification is carried out.Behavioral simulation results show that the correction algorithm can effectively improve the dynamic range and noise performance of pipeline type ADC, and the effective precision can improve about 3 bits s.Then, using the VHDL hardware language, the correction algorithm which has passed the behavior level verification is converted into the integrated RTL (register) level digital circuit, and the code is simulated and verified by using the Modelsim software.The simulation results show that all the errors to be corrected have a correction process and the final correction values are within a reasonable range.Finally, based on 0.13 渭 m standard CMOS process, according to the flow of digital integrated circuit design and EDA design tools such as Design Complier and Encounter, the correction algorithm is converted into the physical realizable digital layout, and the post-simulation verification is carried out.The final digital layout area is 800 渭 m and 600 渭 m, and the post-simulation results are in line with the expected results.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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