基于PCIE IP核的可测试性设计与研究

发布时间：2018-04-11 02:34

本文选题：可测试性设计 + 扫描测试　；参考：《北京工业大学》2015年硕士论文

【摘要】：随着集成电路产业的不断发展,芯片的规模越来越来大,速度越来越快,芯片的测试面临巨大的挑战。如何能够提高芯片的测试质量,降低芯片的测试成本,并且缩短芯片的测试时间,已经成为集成电路领域的研究重点。可测试性设计(Design For Testability,DFT)针对芯片测试中出现的问题,寻求解决方案,其已经成为芯片设计中至关重要的一个环节。详细介绍了可测试性设计的相关原理和概念,并重点分析和讨论了芯片中主要包含的故障类型以及目前业界常用的可测试性设计方法。此外,基于大规模DSP通讯处理芯片华睿2号中的PCIE IP核,针对该芯片的具体结构和特点,制定出一套完整的可测试设计方案,并完成方案的实施,其中包括扫描测试、存储器内建自测试以及实速扫描测试,并且完成芯片的测试向量自动生成以及仿真工作。对PCIE的测试覆盖率、仿真时间、测试时间以及测试功耗进行了深入的研究和讨论,并针对PCIE可测试性设计的要求,完成以上几个方面的优化。其中,通过修复寄存器端口不可控以及存储器周围阴影逻辑不可测的方法,将扫描测试的测试覆盖率提升至98.16%;通过扫描压缩、精简测试向量以及并行仿真的方法,将扫描测试的仿真时间和测试时间分别降至0.15小时和196.780ms;通过优化测试向量无关位以及加入组合逻辑门控技术的方法,将扫描测试功耗降至99.4mW,并且通过加入IEEE P1500结构,将华睿2号芯片顶层的扫描测试峰值功耗较优化前降低了86%。除此之外,基于TSMC 45nm工艺,完成了PCIE的物理设计,最终面积为3.866mm×1.945mm。最后,基于对PCIE的研究,总结出一套完整的包含了可测试性设计的芯片设计流程,并重点总结了可测试性设计流程中的各个环节。
[Abstract]:With the development of IC industry, the scale and speed of chips are becoming larger and faster.How to improve the quality of the chip test, reduce the cost of the chip test, and shorten the test time of the chip, has become the focus of research in the field of integrated circuits.Testability Design For Testability For (DFT) has become an important part of chip design, which aims at the problems in chip testing and seeks solutions.The related principles and concepts of testability design are introduced in detail, and the main fault types contained in the chip are analyzed and discussed in detail, as well as the commonly used testability design methods in the industry at present.In addition, based on the PCIE IP core in the large-scale DSP communication processing chip Hua Rui 2, according to the specific structure and characteristics of the chip, a complete testability design scheme is developed, and the implementation of the scheme, including scanning test, is completed.Memory built-in test and real speed scan test, and complete the chip test vector automatic generation and simulation work.The test coverage, simulation time, test time and test power consumption of PCIE are studied and discussed in depth, and the above aspects are optimized according to the requirements of PCIE testability design.Among them, by repairing the uncontrollable register port and untestable shadow logic around the memory, the test coverage rate of scanning test is increased to 98.160.The method of scanning compression, reducing test vector and parallel simulation is used.The simulation time and test time of scanning test are reduced to 0.15 hours and 196.780ms respectively, the power consumption of scanning test is reduced to 99.4mW by optimizing test vector independent bit and adding combinational logic gating technology, and the power consumption of scanning test is reduced to 99.4mW by adding IEEE P1500 structure.The peak power consumption of the scan test at the top of Hua Rui 2 chip is 86% lower than that before optimization.In addition, based on TSMC 45nm process, the physical design of PCIE is completed, and the final area is 3.866mm 脳 1.945mm.Finally, based on the research of PCIE, a complete set of chip design flow including testability design is summarized, and each link of testability design flow is emphatically summarized.
【学位授予单位】：北京工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407

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