可配置的众核结构验证系统的研究与实现

发布时间：2018-04-11 06:03

本文选题：高通量 + 众核处理器　；参考：《中国科学院大学(工程管理与信息技术学院)》2015年硕士论文

【摘要】：随着以社交网络、云计算和网络多媒体为代表的新型网络应用的出现,人们需要处理的数据量越来越大,而当前数据中心采用面向通用计算领域的处理器,在结构设计时并未充分考虑到高吞吐、强实时、低延迟和易扩展等高通量应用领域的典型特征。所以需要设计一种适合处理高通量计算的处理器,而且需要找到一种具备高吞吐、强实时、低延迟和易扩展的片内互联结构。由于速度,精度,以及灵活性的限制,普通的验证方法以及验证平台无法完成对高通量众核处理器的验证需求。本文提出一种灵活的可配置的FPGA (Field Programmable Gate Array)验证平台,利用多块FPGA板卡通过高速线缆连在一起实现容量可配置,互联方式可配置,连线长度可配置等,来完成对高通量众核处理器内部结构的研究和验证。本文完成的主要工作包括：(1)在充分考虑验证平台的灵活性的基础上,保证验证平台的可行性,以及可靠性和稳定性,设计出整个可配置验证平台的硬件电路部分。(2)基于Xilinx的7系列FPGA的IP (Intellectual Property)核设计出高速的DDR (Double Data Rate)控制器和PCI Express控制器,并实现DMA (Direct Memory Access)功能。(3)在验证平台上面实现高通量众核处理器的模块级的验证工作。(4)实现高通量众核芯片的系统级验证工作并在整个系统上面运行应用程序。本文设计和实现的可配置的众核结构验证系统已经用于国家核高基项目中,为实现高通量芯片的结构研究提供了可靠的平台。
[Abstract]:With the emergence of new network applications, such as social networks, cloud computing and network multimedia, the amount of data that people need to deal with is increasing.The typical characteristics of high throughput applications such as high throughput, strong real time, low delay and easy expansion are not fully taken into account in structural design.Therefore, we need to design a processor suitable for high throughput computing, and find a high throughput, strong real-time, low delay and easy to expand the on-chip interconnection architecture.Due to the limitations of speed, precision, and flexibility, common verification methods and verification platforms can not meet the verification requirements for high-throughput multi-core processors.In this paper, a flexible and configurable FPGA Field Programmable Gate Array-based verification platform is proposed. By using multiple FPGA boards connected by high-speed cables and cables, the capacity can be configured, the interconnection mode can be configured, and the length of the connection can be configured, etc.To complete the research and verification of the internal structure of high throughput multicore processor.The main work accomplished in this paper includes: 1) ensuring the feasibility, reliability and stability of the verification platform on the basis of fully considering the flexibility of the verification platform.The hardware circuit of the whole configurable verification platform is designed. (2) based on the Xilinx 7 series FPGA IP intellectual property core, the high speed DDR double Data repeat controller and PCI Express controller are designed.And implement DMA Direct Memory access. 3) implement the module level verification of high-throughput multi-core processor on the verification platform) realize the system-level verification of high-throughput multi-core chip and run the application program on the whole system.The configurable multi-core structure verification system designed and implemented in this paper has been used in the national nuclear high-base project, which provides a reliable platform for the structure research of high-throughput chips.
【学位授予单位】：中国科学院大学(工程管理与信息技术学院)
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791

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