基于硅通孔绑定后三维芯片测试调度优化方案

发布时间：2018-04-15 13:16

本文选题：三维芯片 + 装箱问题　；参考：《计算机工程与科学》2017年03期

【摘要】：三维芯片(3D-SIC)通过硅通孔TSV技术实现电路的垂直互连,有效提高了系统集成度和整体性能。由于三维芯片测试中,用于测试的引脚数和TSV数目以及测试时功耗的限制都对测试时间有很大的影响,拟提出一种装箱问题思想的测试方案,针对每层只有一个晶片的"单塔"结构和每层有多个晶片的"多塔"结构进行测试调度优化。该优化方案在控制测试引脚数、测试TSV数目与测试功耗的同时,能有效缩短测试时间。实验结果表明,与同类方案相比,在多种限制条件和不同结构中,都有着显著的优化结果。其中"单塔"最高优化45.28%的测试时间,"多塔"最高优化了27.78%的测试时间。
[Abstract]:Three-dimensional chip 3D-SICs realize the vertical interconnection of circuits by silicon through hole TSV technology, which effectively improves the system integration and overall performance.Because the number of pins and TSV used for testing and the limitation of power consumption have great influence on the test time in 3D chip testing, a test scheme based on packing problem is proposed.The test scheduling is optimized for the "single tower" structure with only one chip per layer and the "multi-tower" structure with multiple wafers on each floor.This optimization scheme can effectively shorten the test time while controlling the number of test pins, the number of test TSV and the test power consumption.The experimental results show that, compared with the similar schemes, there are significant optimization results in a variety of constraints and different structures.The test time of "single tower" is 45.28% and that of "multi-tower" is 27.78%.
【作者单位】：合肥工业大学计算机与信息学院;合肥工业大学电子科学与应用物理学院;
【基金】：国家自然科学基金(61674048,61474036,61371025,61574052)
【分类号】：TN407

【参考文献】