采用改进型Fibonacci序列DAC设计技术研究

发布时间：2018-04-15 19:00

本文选题：数模转换器 + 分段式电流舵　；参考：《苏州大学》2015年硕士论文

【摘要】：随着信息技术的高速发展,数字通信系统在信息传输领域的比重日益加大,数模转换器(DAC)作为其中的关键部件之一,其性能的要求越来越高。其中高速、高分辨率和宽带DAC逐渐成为研究的热门方向。电流舵DAC因为其结构本征高速特性和良好的驱动能力,被广泛运用在高速高精度领域。然而,影响电流舵DAC特性的因素有很多,这给芯片设计带来一定的困难。本文针对电流舵DAC设计中的一些难点,对其关键技术进行改进和验证。采用SMIC 0.13μm CMOS工艺,设计了一种12位100MS/s分段式电流舵DAC。在分析、优化和比较四种编码方式的基础上,折衷考虑毛刺、面积和功耗,最终确定采用6+6分段结构。高6位为温度计码,低6位为改进型Fibonacci序列。整体电路由数字和模拟部分组成,具有双通道输出,在1.2V/3.3V(数字/模拟)双电源供电下,满摆幅输出电流为20m A,DAC总面积为0.263mm2。模拟部分设计中,电流镜采用PMOS的Cascode结构来提高其输出阻抗,采用差分形式的开关以保证电流通路始终存在并提高输出摆幅,在其输出端接有伪管来减小时钟馈通效应。数字部分设计中,由于低6位的改进型Fibonacci序列DAC需要将6位数字信号转换成7位数字信号单元,因而需要6-7的译码器。经过真值表、逻辑表达式以及分组方案的不断优化,将低6位分为3+3,其中最低3位分别表示这7位数字单元,通过中间3位控制8-1选择器,最终分得7组不同的译码器,输出的信号交由锁存器进行同步、去抖以及增强开关的驱动能力。对DAC原理图的设计和仿真都是基于Cadence Spectre软件平台,版图设计和验证则是利用Cadence Virtuoso、Calibre和Matlab软件。后仿结果为:INL为±0.3595LSB,DNL为±0.3039LSB,正弦输入信号为15.625MHz、48.4375MHz时差分输出的SFDR分别为73.92154d B和73.15604d B,总功耗为78.54m W(数字部分为10.56m W,模拟部分为67.98m W)。仿真结果表明,采用改进型Fibonacci序列DAC性能优越,可广泛用于无线通信领域。
[Abstract]:With the rapid development of information technology, the proportion of digital communication system in the field of information transmission is increasing. As one of the key components, the performance of digital to analog converter (DAC) is becoming more and more important.Among them, high-speed, high-resolution and wide-band DAC gradually become the hot research direction.The current steering DAC is widely used in high speed and high precision fields because of its intrinsic high speed characteristic and good driving ability.However, there are many factors that affect the DAC characteristics of the current rudder, which brings some difficulties to the chip design.This paper improves and verifies the key technology of current rudder DAC design.Using SMIC 0.13 渭 m CMOS process, a 12-bit 100MS/s segmented current rudder was designed.Based on the analysis, optimization and comparison of the four coding methods, a compromise of burr, area and power consumption is taken into account, and a 66 segment structure is finally adopted.The high 6 bits are thermometer codes and the low 6 bits are modified Fibonacci sequences.The whole circuit is composed of digital and analog parts and has two output channels. Under the power supply of 1.2V / 3.3V (digital / analog) dual power supply, the total area of 20m ADA DAC with full swing output current is 0.263mm ~ 2.In the analog design, the current mirror adopts the Cascode structure of PMOS to improve the output impedance, uses the differential switch to ensure the current path always exists and increases the output swing, and the pseudo-tube is connected to the output to reduce the clock feed-through effect.In the design of the digital part, the 6-7 decoder is needed because the 6-bit modified Fibonacci sequence DAC needs to convert 6-bit digital signal into 7-bit digital signal unit.Through the continuous optimization of truth table, logical expression and grouping scheme, the low 6 bits are divided into 3 3 bits, in which the lowest 3 bits represent the 7 digit units respectively. Through the intermediate 3 bits control 8 1 selector, 7 different decoders are obtained.The output signal is synchronized by the latch, detrembled and enhanced in the drive capacity of the switch.The design and simulation of DAC schematic are based on Cadence Spectre software platform, and layout design and verification are based on Cadence Virtuoso calibre and Matlab software.The following simulation results show that: INL is 卤0.3595LSB-DNL 卤0.3039LSB.The sinusoidal input signal is 15.625MHz, 48.4375MHz, the SFDR is 73.92154dB and 73.15604dB, the total power consumption is 78.54mWW (digital part is 10.56mWW, analog part is 67.98mWN).The simulation results show that the improved Fibonacci sequence DAC has excellent performance and can be widely used in wireless communication field.
【学位授予单位】：苏州大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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