一种折叠插值模数转换器的建模与设计

发布时间：2018-04-16 13:04

本文选题：模数转换器 + 折叠　；参考：《合肥工业大学》2015年硕士论文

【摘要】：高速ADC在无线通讯和雷达卫星等高速信号处理领域有着广泛的应用和研究前景。在各类ADC中,全并行Flash ADC速度最快,但随着精度的增加系统规模呈指数型增长。折叠插值ADC改进了原有的全并行结构,利用折叠和插值等预处理电路实现了粗量化和细量化过程的同步进行。减小了系统规模且保证了原有结构的高速度特性。因此在高速ADC领域具有实际研究价值并成为研究热点。本文首先根据折叠插值ADC的基本原理,深入研究和分析了系统的工作过程和实现方式,详细阐述了折叠技术和插值技术的基本原理和电路结构。根据系统精度和速度以及电路规模的设计要求,选择了差分对折叠和电压插值结构,并确定了3位粗量化和5位细量化结构来实现系统8位精度。其次,根据原理进行系统级建模,验证了折叠插值ADC工作原理及其架构选择的可行性。并分析系统各模块及非理想因素,指导实际电路的设计。最后,在原理分析和系统级建模的基础上,设计了折叠插值ADC的部分关键电路并完成仿真和验证。其中包括差分对结构预放大器的设计,以降低比较器输入失调的影响。预放大器和动态锁存比较器的结合即可完成粗量化过程。差分对折叠电路能产生线性度较好的折叠信号并抑制共模干扰。电压插值电路通过简单的电阻插值结构产生更多折叠信号以提高系统的线性度。位同步电路保证了粗量化和细量化信号的同步输出减小编码误差。本文基于TSMC 0.18um CMOS工艺,1.8V电源电压,利用Cadence的Spectre软件进行电路设计和仿真。仿真结果表明,所设计的折叠插值ADC在250MHz采样频率,121.09MHz输入信号下有效位数达到7.85bit,在500MHz采样频率,101.56MHz输入信号下有效位数达7.53bit。
[Abstract]:High-speed ADC has a wide range of applications and research prospects in high-speed signal processing such as wireless communications and radar satellites.Among all kinds of ADC, the speed of full parallel Flash ADC is the fastest, but the system scale increases exponentially with the increase of precision.The folding interpolation ADC improves the original full parallel structure and uses the preprocessing circuits such as folding and interpolation to realize the synchronization of coarse quantization and fine quantization.The system size is reduced and the high speed characteristic of the original structure is guaranteed.Therefore, it has practical research value in the field of high speed ADC and has become a research hotspot.In this paper, according to the basic principle of folding interpolation ADC, the working process and realization of the system are studied and analyzed, and the basic principle and circuit structure of folding and interpolation technology are described in detail.According to the design requirements of system precision, speed and circuit scale, differential pair folding and voltage interpolation structures are selected, and 3-bit coarse quantization and 5-bit fine quantization structures are determined to realize the system 8-bit precision.Secondly, system-level modeling is carried out according to the principle, which verifies the feasibility of folding and interpolating ADC working principle and architecture selection.The system modules and non-ideal factors are analyzed to guide the design of practical circuits.Finally, on the basis of principle analysis and system-level modeling, some key circuits of folded interpolated ADC are designed and simulated and verified.This includes the design of differential preamplifiers to reduce the effect of comparator input misalignment.The combination of preamplifier and dynamic latch comparator can complete the coarse quantization process.Differential pair folding circuit can produce good linearity of folding signal and suppress common-mode interference.The voltage interpolation circuit generates more folding signals through a simple resistance interpolation structure to improve the linearity of the system.The bit synchronization circuit ensures the synchronization output of coarse quantization and fine quantization signal to reduce the coding error.Based on the 1.8V power supply voltage of TSMC 0.18um CMOS process, the circuit design and simulation are carried out by Spectre software of Cadence.The simulation results show that the effective bit number of the designed folded interpolated ADC is 7.85 bit at 121.09 MHz 250MHz sampling frequency and 7.53 bit at 500MHz sampling frequency 101.56 MHz input signal.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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