专用于SRAM失配特性研究的可寻址测试芯片的研究与实现

发布时间：2018-04-17 11:53

本文选题：集成电路制造 + 成品率　；参考：《浙江大学》2015年硕士论文

【摘要】：随着集成电路制造的工艺尺寸不断减小,集成电路制造工艺越来越复杂,由缺陷引起的成品率问题渐趋严重。晶体管的失配问题也因为工艺尺寸的减小而变得严重,失配问题对集成电路的性能的影响非常明显,从而会造成成品率的问题。SRAM单元中的晶体管由于尺寸更小,设计更加紧凑,设计规则更严格等问题,SRAM单元中晶体管的失配问题更加严峻。测试芯片作为监测制造工艺缺陷,评估产品可靠性和提取器件工艺参数的工具,对提升集成电路制造工艺成品率起着举足轻重的作用。可寻址测试芯片由于在放置测试结构的数量上具有非常大的优势而成为测试芯片分支的研究热点。本文围绕更高面积利用率和测试精度的专用于SRAM失配特性研究的可寻址测试芯片展开了研究： 1)针对SRAM的特殊结构,提出了一种专用于SRAM单元中晶体管对的失配特性研究的测试结构的设计方法。对于SRAM单元中的PD、PG和PU三种类型的晶体管对,分别设计了其对应的测试结构。这些测试结构都是在原始的SRAM单元版图的基础上修改而得到的,修改的原则是保持其前端设计不变,修改部分金属绕线隔离待测晶体管与其他晶体管的连接,并且修改后的测试结构版图保持对称。 2)针对专用于SRAM单元晶体管对的失配特性的测试设计了放置在划片槽的可寻址测试芯片。该方法实现了在68×2381um2的测试芯片面积内放置120对DUT,并能够准确的测量每个DUT的晶体管性能参数：饱和状态下的漏极和源极之间的电流、亚阈值电流、饱和状态下的阈值电压和线性状态下的阈值电压。这种测试芯片在28nm CMOS工艺下进行了流片,并对其进行了测试,验证了这种设计方法的可行性和测试精度。
[Abstract]:With the continuous reduction of the process size of IC manufacturing, the IC manufacturing process is becoming more and more complex, and the problem of yield caused by defects is becoming more and more serious.The problem of transistor mismatch also becomes serious because of the decrease of process size. The effect of mismatch problem on the performance of integrated circuit is very obvious, which will result in the yield problem. The transistor in SRAM cell is smaller in size and more compact in design.More strict design rules and other problems, SRAM cells in the transistor mismatch more serious.As a tool for monitoring manufacturing process defects, evaluating product reliability and extracting device process parameters, the test chip plays an important role in improving the production rate of integrated circuit manufacturing process.Addressable test chips have become the research focus of test chips due to their great advantages in the number of test structures.This paper focuses on the addressable test chip which is dedicated to the study of SRAM mismatch characteristics with higher area utilization ratio and test accuracy.1) aiming at the special structure of SRAM, a design method of test structure for the study of mismatch characteristics of transistor pairs in SRAM cells is presented.The corresponding test structures are designed for three types of transistors, PDPG and pu, in SRAM cells.These test structures were all modified on the basis of the original SRAM cell layout. The principle of the modification was to keep its front-end design unchanged, and to modify the connection of some metal wire wound isolated transistors to other transistors.And the revised layout of the test structure remains symmetrical.2) the addressable test chip is designed for the mismatch characteristic of SRAM unit transistor pair.In this method, 120 pairs of DUTs are placed in the area of 68 脳 2381um2 test chip, and the transistor performance parameters of each DUT can be accurately measured: the current between drain and source in saturated state, subthreshold current, etc.Threshold voltage in saturation state and threshold voltage in linear state.The test chip is carried out in 28nm CMOS process and tested. The feasibility and accuracy of the design method are verified.
【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN405

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